Thyristors logic level for RCD/ GFI/ LCCB applications

GENERAL DESCRIPTION Glass passivated, sensitive gate thyristors in a plastic envelope, intended for use in Residual Current Devices/ Ground Fault Interrupters/Leakage Current Circuit Breakers (RCD/ GFI/ LCCB) applications where a minimum IGTlimit is needed. These devices may be interfaced direc

文件：43 Kbytes 页数：6 Pages

PHI

PHI

Thyristors logic level for RCD/ GFI/ LCCB applications

恩XP

20-bit bus-interface D-type flip-flop; positive-edge trigger 3-State

DESCRIPTION The 74ABT16821A high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. FEATURES • 20-bit positive-edge triggered register • Multiple VCC and GND pins minimize switching noise • Live insertion/extraction permitte

文件：80.77 Kbytes 页数：10 Pages

PHI

PHI

20-bit bus-interface D-type flip-flop; positive-edge trigger 3-State

DESCRIPTION The 74ABT16821A high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. FEATURES • 20-bit positive-edge triggered register • Multiple VCC and GND pins minimize switching noise • Live insertion/extraction permitte

文件：80.77 Kbytes 页数：10 Pages

PHI

PHI

18-bit bus interface D-type flip-flop with reset and enable 3-State

DESCRIPTION The 74ABT16823A 18-bit bus interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity. FEATURES • Two sets of high speed parallel registers with positive edge

文件：86.11 Kbytes 页数：12 Pages

PHI

PHI

18-bit bus interface D-type flip-flop with reset and enable 3-State

DESCRIPTION The 74ABT16823A 18-bit bus interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity. FEATURES • Two sets of high speed parallel registers with positive edge

文件：86.11 Kbytes 页数：12 Pages

PHI

PHI

20-bit buffer/line driver, non-inverting 3-State

DESCRIPTION The 74ABT16827A high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. FEATURES • Multiple VCC and GND pins minimize switching noise • Live insertion/extraction permitted • 3-State output buffers • Power-up 3-S

文件：73.93 Kbytes 页数：10 Pages

PHI

PHI

20-bit buffer/line driver, non-inverting 3-State

DESCRIPTION The 74ABT16827A high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. FEATURES • Multiple VCC and GND pins minimize switching noise • Live insertion/extraction permitted • 3-State output buffers • Power-up 3-S

文件：73.93 Kbytes 页数：10 Pages

PHI

PHI

20-bit bus interface latch 3-State

DESCRIPTION The 74ABT16841A Bus interface latch is designed to provide extra data width for wider data/address paths of buses carrying parity. FEATURES • High speed parallel latches • Live insertion/extraction permitted • Extra data width for wide address/data paths or buses carrying parity

文件：82.19 Kbytes 页数：10 Pages

PHI

PHI

20-bit bus interface latch 3-State

DESCRIPTION The 74ABT16841A Bus interface latch is designed to provide extra data width for wider data/address paths of buses carrying parity. FEATURES • High speed parallel latches • Live insertion/extraction permitted • Extra data width for wide address/data paths or buses carrying parity

文件：82.19 Kbytes 页数：10 Pages

PHI

PHI