18-bit bus interface D-type flip-flop with reset and enable 3-State

DESCRIPTION The 74ABT16823A 18-bit bus interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity. FEATURES • Two sets of high speed parallel registers with positive edge

文件：86.11 Kbytes 页数：12 Pages

PHI

PHI

18-bit bus interface D-type flip-flop with reset and enable 3-State

恩XP

18-bit bus interface D-type flip-flop with reset and enable 3-State

DESCRIPTION The 74ABT16823A 18-bit bus interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity. FEATURES • Two sets of high speed parallel registers with positive edge

文件：86.11 Kbytes 页数：12 Pages

PHI

PHI

18-bit bus interface D-type flip-flop with reset and enable 3-State

DESCRIPTION The 74ABT16823A 18-bit bus interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity. FEATURES • Two sets of high speed parallel registers with positive edge

文件：86.11 Kbytes 页数：12 Pages

PHI

PHI

~15째 spot beam

文件：2.80841 Mbytes 页数：6 Pages

LEDIL