BCM84328数据手册集成电路（IC）的控制器规格书PDF

描述 Description

Low-power, low-latency PHY integrating retimer and equalizer functions supporting 40 Gigabit Ethernet (GbE) and 10 GbE applications. In 40G mode, the BCM84328 supports two full-duplex 40 GbE ports (XLPPI-to-XLAUI/KR4) for SR4, LR4 and copper CR4 QSFP+ line-card applications. In 10G mode, the BCM84328 supports eight full-duplex 10 GbE ports (SFI-to-XFI/KR) for SR, LR and copper CR SFP+ line-card applications. On-chip clock synthesis is performed by a single low-cost 156.25 MHz reference clock via high-frequency, low-jitter, phase-locked loops (PLLs). Individual clock recovery is performed on the device by synchronizing directly to the respective incoming data streams.

特性 Features

·Dual 40G channels with two XLPPI-to-XLAUI/KR4 ports supporting SR4/LR4/CR4 QSFP+ retimer/equalization applications
· 10G Mode with eight independent 10G/1G SFI-to-XFI/KR channels supporting SR/LR/CR SFP+ retimer/equalization applications. Supports intermix of 1G and 10G operations on a per-lane basis
·Low-latency design
·Low-power retimer/equalizer PHY (~300 mW per 10G bidirectional port)