BCM8154数据手册集成电路（IC）的驱动器接收器收发器规格书PDF

描述 Description

Fully integrated MSA-compatible multirate SONET/SDH/10-GbE/Fibre-Channel/FEC transceiver operating at 9.953 Gb/s, 10.3125 Gb/s, 10.519 Gb/s, 10.664 Gb/s, 10.709 Gb/s, 11.095 Gb/s, 11.318 Gb/s or 11.352 Gb/s. On-chip clock synthesis is performed by the high-frequency, low-jitter PLL, allowing the use of a low-frequency reference clock selectable to the line rate divided by either 16 or 64. The 10G TX clock phase is adjustable for clocked driver applications. An on-chip phase detector and charge pump plus external VCXO implement a cleanup PLL. The cleanup PLL can be used to attenuate jitter on the CDR recovered clock for loop timing applications or to provide a low-jitter reference clock from a noisy system clock. Any SONET timing mode may be configured with the BCM8154 timing architecture, making the timing mode and cleanup functions user-selectable in the field rather than during manufacturing, therefore simplifying engineering and manufacturing requirements.

特性 Features

·Fully integrated multirate CDR, DEMUX, MUX, CMU
·300-pin Multisource Agreement (MSA) compatible
·Compliant to OIF, Telcordia®, ITU-T, XFI specification and IEEE 802.3ae standards
·Input sensitivity 10 mV peak-to-peak