BCM81181数据手册集成电路（IC）的驱动器接收器收发器规格书PDF

描述 Description

The Broadcom BCM81181 is a single-chip, low-power, low-latency PAM-4 PHY that integrates retimer and equalizer functions to support 400GbE applications. In 400GbE mode, the BCM81181 retimes, adds FEC (optional), and equalizes 8 × 50G PAM-4 host-side signals into 8 × 50G PAM-4 line-side signals, which drive optical PAM-4 links inside next-generation modules, including QSFPDD and OSFP. The BCM81181 is compliant to IEEE standards with KP4 FEC and FEC bypass capability. On-chip clock synthesis is performed by a low-cost 156.25 MHz reference clock via high-frequency, low-jitter phase-locked loops (PLLs). The BCM81181 is fabricated in advanced low-power 16 nm CMOS technology and is available in a RoHS-compliant package.

特性 Features

• 400GbE (8 × 50G PAM-4) PHY
• Host side: 8 × 50G PAM-4
• Line side: 8 × 50G PAM-4
• IEEE 802.3bs and 802.3cd compliance
• IEEE 400GAUI-8 PAM4 C2M compliant  
• Integrated host side AC-coupling caps 
• Line-side and client-side loopbacks
• Supports reaches for MMF/SMF fiber links 
• Low-power 16 nm CMOS design