ECL/PECL 첨 2 Divider

DESCRIPTION The AZ10/100EL32 is an integrated ÷2 divider. The reset pin is asynchronous and is asserted on the rising edge. Upon power-up, the internal flip-flop will attain a random logic state; the reset allows for the synchronization of multiple EL32’s in a system. The EL32 provides a VBB

文件：104.2 Kbytes 页数：6 Pages

AZM

ECL/PECL 첨 2 Divider

DESCRIPTION The AZ10/100EL32 is an integrated ÷2 divider. The reset pin is asynchronous and is asserted on the rising edge. Upon power-up, the internal flip-flop will attain a random logic state; the reset allows for the synchronization of multiple EL32’s in a system. The EL32 provides a VBB

文件：104.21 Kbytes 页数：6 Pages

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첨2 Divider

Description The MC10EL/100EL32 is an integrated ÷2 divider. The differential clock inputs and the VBB allow a differential, single-ended or AC coupled interface to the device. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions,

文件：76.72 Kbytes 页数：3 Pages

ONSEMI

安森美半导体

5V ECL 첨2 Divider

文件：155 Kbytes 页数：9 Pages

ONSEMI

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Divider

文件：171.35 Kbytes 页数：8 Pages

ONSEMI

安森美半导体