MOSFET

ATC Semi

RMI Alchemy™ Au1250™ Media Processor

Primary Features Customized MIPS32® Core • 333, 400, 500, 600 and 700MHz • 32-bit architecture • 16KB instruct + 16KB data caches • High-speed multiply-accumulate (MAC) and divide unit • 1.2V core, 3.3V I/O Media Acceleration Engine (MAE) • Support for MPEG1, 2, 4, and WMV9 scaled up to 10

文件：1.02289 Mbytes 页数：5 Pages

ETCList of Unclassifed Manufacturers

未分类制造商

2A Sink/Source Bus Termination Regulator

 GENERAL DESCRIPTION The AX1250ES is a simple, cost-effective and high-speed linear regulator designed to generate termination voltage in double data rate (DDR) memory system to comply with the JEDEC SSTL_2 and SSTL_18 or other specific interfaces such as HSTL, SCSI-2 and SCSI-3 etc. devices req

文件：753.8 Kbytes 页数：10 Pages

AXELITE

亚瑟莱特

2A Sink/Source Bus Termination Regulator

 GENERAL DESCRIPTION The AX1250ES is a simple, cost-effective and high-speed linear regulator designed to generate termination voltage in double data rate (DDR) memory system to comply with the JEDEC SSTL_2 and SSTL_18 or other specific interfaces such as HSTL, SCSI-2 and SCSI-3 etc. devices req

文件：753.8 Kbytes 页数：10 Pages

AXELITE

亚瑟莱特