4 Meg x 16 SDRAM Synchronous DRAM Memory

FEATURES • Extended Testing Over -55°C to +125° C and Industrial Temp -40°C to 85° C • WRITE Recovery ( tWR/ tDPL) tWR = 2 CLK • Fully synchronous; all signals registered on positive edge of system clock • Internal pipelined operation; column address can be changed every clock c

文件：1.15056 Mbytes 页数：50 Pages

AUSTIN

4 Meg x 16 SDRAM Synchronous DRAM Memory

文件：568.19 Kbytes 页数：50 Pages

AUSTIN

4 Meg x 16 SDRAM

Austin Semiconductor

4 Meg x 16 SDRAM Synchronous DRAM Memory

FEATURES • Extended Testing Over -55°C to +125° C and Industrial Temp -40°C to 85° C • WRITE Recovery ( tWR/ tDPL) tWR = 2 CLK • Fully synchronous; all signals registered on positive edge of system clock • Internal pipelined operation; column address can be changed every clock c

文件：1.15056 Mbytes 页数：50 Pages

AUSTIN

4 Meg x 16 SDRAM Synchronous DRAM Memory

FEATURES • Extended Testing Over -55°C to +125° C and Industrial Temp -40°C to 85° C • WRITE Recovery ( tWR/ tDPL) tWR = 2 CLK • Fully synchronous; all signals registered on positive edge of system clock • Internal pipelined operation; column address can be changed every clock c

文件：1.15056 Mbytes 页数：50 Pages

AUSTIN

4 Meg x 16 SDRAM Synchronous DRAM Memory

FEATURES • Extended Testing Over -55°C to +125° C and Industrial Temp -40°C to 85° C • WRITE Recovery ( tWR/ tDPL) tWR = 2 CLK • Fully synchronous; all signals registered on positive edge of system clock • Internal pipelined operation; column address can be changed every clock c

文件：1.15056 Mbytes 页数：50 Pages

AUSTIN

4 Meg x 16 SDRAM Synchronous DRAM Memory

FEATURES • Extended Testing Over -55°C to +125° C and Industrial Temp -40°C to 85° C • WRITE Recovery ( tWR/ tDPL) tWR = 2 CLK • Fully synchronous; all signals registered on positive edge of system clock • Internal pipelined operation; column address can be changed every clock c

文件：1.15056 Mbytes 页数：50 Pages

AUSTIN

4 Meg x 16 SDRAM Synchronous DRAM Memory

FEATURES • Extended Testing Over -55°C to +125° C and Industrial Temp -40°C to 85° C • WRITE Recovery ( tWR/ tDPL) tWR = 2 CLK • Fully synchronous; all signals registered on positive edge of system clock • Internal pipelined operation; column address can be changed every clock c

文件：1.15056 Mbytes 页数：50 Pages

AUSTIN

4 Meg x 16 SDRAM Synchronous DRAM Memory

FEATURES • Extended Testing Over -55°C to +125° C and Industrial Temp -40°C to 85° C • WRITE Recovery ( tWR/ tDPL) tWR = 2 CLK • Fully synchronous; all signals registered on positive edge of system clock • Internal pipelined operation; column address can be changed every clock c

文件：1.15056 Mbytes 页数：50 Pages

AUSTIN

4 Meg x 16 SDRAM Synchronous DRAM Memory

FEATURES • Extended Testing Over -55°C to +125° C and Industrial Temp -40°C to 85° C • WRITE Recovery ( tWR/ tDPL) tWR = 2 CLK • Fully synchronous; all signals registered on positive edge of system clock • Internal pipelined operation; column address can be changed every clock c

文件：1.15056 Mbytes 页数：50 Pages

AUSTIN