AM3892中文资料Sitara 处理器：Arm Cortex-A8、HDMI数据手册TI规格书

描述 Description

The AM389x Sitara ARM processors are a highly integrated, programmable platform that leverages TI's Sitara technology to meet the processing needs of the following applications: single-board computing, network and communications processing, industrial automation, human machine interface, and interactive point-of-service kiosks.The device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance through the maximum flexibility of a fully integrated mixed processor solution. The device combines high-performance ARM processing with a highly integrated peripheral set. The ARM Cortex-A8 32-bit RISC processor with NEON floating-point extension includes: 32KB of instruction cache; 32KB of data cache; 256KB of L2 cache; and 64KB of RAM.The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each peripheral, see the related sections in this document and the associated peripheral reference guides. The peripheral set includes: HD video processing subsystem (HDVPSS), which provides output of simultaneous HD and SD analog video and dual HD video inputs; up to two Gigabit Ethernet MACs (10 Mbps,100, Mbps, 1000 Mbps) with GMII and MDIO interface; two USB ports with integrated 2.0 PHY; PCIe port x2 lanes GEN2 compliant interface, which allows the device to act as a PCIe root complex or device endpoint; one 6-channel McASP audio serial port (with DIT mode); two dual-channel McASP audio serial ports (with DIT mode); one McBSP multichannel buffered serial port; three UARTs with IrDA and CIR support; SPI serial interface; SD and SDIO serial interface; two I2C master and slave interfaces; up to 64 GPIO pins; seven 32-bit timers; system watchdog timer; dual DDR2 and DDR3 SDRAM interface; flexible 8-bit and 16-bit asynchronous memory interface; and up to two SATA interfaces for external storage on two disk drives or more with the use of a port multiplier. The device also includes an SGX530 3D graphics engine (available only on the AM3894 device) to off-load many video and imaging processing tasks from the core. Additionally, the device has a complete set of development tools for the ARM, including C compilers and a Microsoft Windows debugger interface for visibility into source code execution.The device package has been specially engineered with Via Channel technology. This technology allows use of 0.8-mm pitch PCB feature sizes in this 0.65-mm pitch package, and substantially reduces PCB costs. Via Channel technology also allows PCB routing in only two signal layers due to the increased layer efficiency of the Via Channel BGA technology.

特性 Features

• High-Performance Sitara ARM Microprocessors (MPUs)
• Up to 1.20 GHz
• ARM Cortex-A8 Core
• In-Order, Dual-Issue, Superscalar Processor Core
• Supports Integer and Floating Point (VFPv3-IEEE754 Compliant)
• ARM Cortex-A8 Memory Architecture
• 256-KB L2 Cache
• 512KB of On-Chip Memory Controller (OCMC) RAM
• Delivers up to 30 MTriangles per Second
• Direct3D Mobile, OpenGL ES 1.1 and 2.0, OpenVG 1.1, OpenMax API Support
• Programmable HQ Image Anti-Aliasing
• Endianness
• HD Video Processing Subsystem (HDVPSS)
• One 16-Bit or 24-Bit and One 16-Bit Channel
• Two 165-MHz HD Video Display Channels
• Simultaneous SD and HD Analog Output
• Three Graphics Layers
• Dual 32-Bit DDR2 and DDR3 SDRAM Interfaces
• Up to Eight x8 Devices Total
• Dynamic Memory Manager (DMM)
• Enables Efficient 2D Block Accesses
• Optimizes Interlaced Accesses
• One PCI Express (PCIe) 2.0 Port with Integrated PHY
• Configurable as Root Complex or Endpoint
• Serial ATA (SATA) 3.0 Gbps Controller with Integrated PHYs
• Hardware-Assisted Native Command Queuing (NCQ) from up to 32 Entries
• Two 10 Mbps, 100 Mbps, and 1000 Mbps Ethernet MACs (EMAC)
• MII and GMII Media Independent Interfaces
• Dual USB 2.0 Ports with Integrated PHYs
• USB 2.0 High-Speed, Full-Speed, and Low-Speed Host
• General-Purpose Memory Controller (GPMC)
• Up to 6 Chip Selects with up to 256-MB Address Space per Chip Select Pin
• Error Locator Module (ELM) Outside of GPMC to Provide up to 16-Bit and 512-Byte Hardware ECC for NAND
• Enhanced Direct-Memory-Access (EDMA) Controller
• 64 Independent DMA Channels and 8 Quick DMA (QDMA) Channels
• Seven 32-Bit General-Purpose Timers
• Three Configurable UART, IrDA, and CIR Modules
• Supports up to 3.6864 Mbps UART
• One 40-MHz Serial Peripheral Interface (SPI) with Four Chip Selects
• Dual Inter-Integrated Circuit (I2C bus) Ports
• One Six-Serializer Transmit and Receive Port
• DIT-Capable For SDIF and PDIF (All Ports)
• Multichannel Buffered Serial Port (McBSP)
• Two Clock Zones and Two Serial Data Pins
• Real-Time Clock (RTC)
• Up to 64 General-Purpose I/O (GPIO) Pins
• Power, Reset, and Clock Management
• Seven Independent Core Power Domains
• IEEE 1149.1 (JTAG) and IEEE 1149.7 (cJTAG) Compatible
• 40-nm CMOS Technology
• 3.3-V Single-Ended LVCMOS I/Os (Except for DDR3 at 1.5 V, DDR2 at 1.8 V, and DEV_CLKIN at 1.8 V)