丝印：AM2631C；Package：NFBGA；AM263x Sitara™ Microcontrollers

1 Features Processor Cores: • Single, dual, and quad-core Arm® Cortex®-R5F MCU with each core running up to 400 MHz – 16KB I-cache with 64-bit ECC per CPU core – 16KB D-cache with 32-bit ECC per CPU core – 64KB Tightly-Coupled Memory (TCM) with 32- bit ECC per CPU core – Lockstep or Dual-c

文件：2.4283 Mbytes 页数：167 Pages

TI

德州仪器

丝印：AM2631C；Package：NFBGA；AM263x Sitara™ Microcontrollers

1 Features Processor Cores: • Single, dual, and quad-core Arm® Cortex®-R5F MCU with each core running up to 400 MHz – 16KB I-cache with 64-bit ECC per CPU core – 16KB D-cache with 32-bit ECC per CPU core – 64KB Tightly-Coupled Memory (TCM) with 32- bit ECC per CPU core – Lockstep or Dual-c

文件：2.4283 Mbytes 页数：167 Pages

TI

德州仪器

丝印：AM2631C；Package：NFBGA；AM263x Sitara™ Microcontrollers

1 Features Processor Cores: • Single, dual, and quad-core Arm® Cortex®-R5F MCU with each core running up to 400 MHz – 16KB I-cache with 64-bit ECC per CPU core – 16KB D-cache with 32-bit ECC per CPU core – 64KB Tightly-Coupled Memory (TCM) with 32- bit ECC per CPU core – Lockstep or Dual-c

文件：2.4283 Mbytes 页数：167 Pages

TI

德州仪器

丝印：AM2631C；Package：NFBGA；AM263x Sitara™ Microcontrollers

1 Features Processor Cores: • Single, dual, and quad-core Arm® Cortex®-R5F MCU with each core running up to 400 MHz – 16KB I-cache with 64-bit ECC per CPU core – 16KB D-cache with 32-bit ECC per CPU core – 64KB Tightly-Coupled Memory (TCM) with 32- bit ECC per CPU core – Lockstep or Dual-c

文件：2.4283 Mbytes 页数：167 Pages

TI

德州仪器

AM263x Sitara™ Microcontrollers

1 Features Processor Cores: • Single, dual, and quad-core Arm® Cortex®-R5F MCU with each core running up to 400 MHz – 16KB I-cache with 64-bit ECC per CPU core – 16KB D-cache with 32-bit ECC per CPU core – 64KB Tightly-Coupled Memory (TCM) with 32- bit ECC per CPU core – Lockstep or Dual-c

文件：2.4283 Mbytes 页数：167 Pages

TI

德州仪器

AM263x Sitara™ Microcontrollers

1 Features Processor Cores: • Single, dual, and quad-core Arm® Cortex®-R5F MCU with each core running up to 400 MHz – 16KB I-cache with 64-bit ECC per CPU core – 16KB D-cache with 32-bit ECC per CPU core – 64KB Tightly-Coupled Memory (TCM) with 32- bit ECC per CPU core – Lockstep or Dual-c

文件：2.4283 Mbytes 页数：167 Pages

TI

德州仪器