丝印：AHC；Package：VSSOP；2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

Maximum Throughput . . . 140/200 KSPS Built-In Conversion Clock INL/DNL: ±1 LSB Max, SINAD: 72 dB, SFDR: 85 dB, fi = 20 kHz SPI/DSP-Compatible Serial Interface Single Supply: 2.7 Vdc to 5.5 Vdc Rail-to-Rail Analog Input With 500 kHz BW Three Options Available: − TLV2541: Single Channel Inp

文件：893.5 Kbytes 页数：34 Pages

TI

德州仪器

丝印：AHC；Package：VSSOP；2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

Maximum Throughput . . . 140/200 KSPS Built-In Conversion Clock INL/DNL: ±1 LSB Max, SINAD: 72 dB, SFDR: 85 dB, fi = 20 kHz SPI/DSP-Compatible Serial Interface Single Supply: 2.7 Vdc to 5.5 Vdc Rail-to-Rail Analog Input With 500 kHz BW Three Options Available: − TLV2541: Single Channel Inp

文件：893.5 Kbytes 页数：34 Pages

TI

德州仪器

丝印：AHC；Package：VSSOP；2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

Maximum Throughput . . . 140/200 KSPS Built-In Conversion Clock INL/DNL: ±1 LSB Max, SINAD: 72 dB, SFDR: 85 dB, fi = 20 kHz SPI/DSP-Compatible Serial Interface Single Supply: 2.7 Vdc to 5.5 Vdc Rail-to-Rail Analog Input With 500 kHz BW Three Options Available: − TLV2541: Single Channel Inp

文件：893.5 Kbytes 页数：34 Pages

TI

德州仪器

丝印：AHC；Package：VSSOP；2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

Maximum Throughput . . . 140/200 KSPS Built-In Conversion Clock INL/DNL: ±1 LSB Max, SINAD: 72 dB, SFDR: 85 dB, fi = 20 kHz SPI/DSP-Compatible Serial Interface Single Supply: 2.7 Vdc to 5.5 Vdc Rail-to-Rail Analog Input With 500 kHz BW Three Options Available: − TLV2541: Single Channel Inp

文件：893.5 Kbytes 页数：34 Pages

TI

德州仪器

丝印：AHC16244；Package：TSSOP；SNx4AHC16244 16-Bit Buffers/Drivers With 3-State Outputs

1 Features • Members of the Texas Instruments Widebus™ Family • EPIC™ (Enhanced-Performance Implanted CMOS) Process • Operating Range 2-V to 5.5-V VCC • Distributed VCC and GND Pins Minimize High-Speed Switching Noise • Flow-Through Architecture Optimizes PCB Layout • Latch-Up Performance

文件：595.23 Kbytes 页数：25 Pages

TI

德州仪器

丝印：AHC30；Package：SOT762-1；8-input NAND gate

1. General description The 74AHC30; 74AHCT30 is a high-speed Si-gate CMOS device and is pin compatible with Lowpower Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC30; 74AHCT30 provides an 8-input NAND function. 2. Features and benefits • Balanced pr

文件：255.71 Kbytes 页数：16 Pages

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

丝印：AHC30；Package：SOT402-1；8-input NAND gate

1. General description The 74AHC30; 74AHCT30 is a high-speed Si-gate CMOS device and is pin compatible with Lowpower Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC30; 74AHCT30 provides an 8-input NAND function. 2. Features and benefits • Balanced pr

文件：255.71 Kbytes 页数：16 Pages

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

丝印：AHCT16244；Package：TSSOP；SN74AHCT16244 16-Bit Buffers/Drivers With 3-State Outputs

1 Features 1• Members of the Texas Instruments Widebus™ Family • EPIC™ (Enhanced-Performance Implanted CMOS) Process • Inputs are TTL-Voltage Compatible • Distributed VCC and GND Pins Minimize High-Speed Switching Noise • Flow-Through Architecture Optimizes PCB Layout • Latch-Up Performan

文件：560.58 Kbytes 页数：23 Pages

TI

德州仪器

丝印：AHCT16245；Package：TSSOP；SN74AHCT16245 16-Bit Bus Transceivers With 3-State Outputs

1 Features • Members of Texas Instruments’ Widebus™ Family • Inputs are TTL-Voltage Compatible • Distributed VCC and GND Pins Minimize High-Speed Switching Noise • Flow-Through Architecture Optimizes PCB Layout • Latch-Up Performance Exceeds 250 mA Per JESD 17 2 Applications • Telecom

文件：569.4 Kbytes 页数：24 Pages

TI

德州仪器

丝印：AHCT16245；Package：SSOP；SN74AHCT16245 16-Bit Bus Transceivers With 3-State Outputs

1 Features • Members of Texas Instruments’ Widebus™ Family • Inputs are TTL-Voltage Compatible • Distributed VCC and GND Pins Minimize High-Speed Switching Noise • Flow-Through Architecture Optimizes PCB Layout • Latch-Up Performance Exceeds 250 mA Per JESD 17 2 Applications • Telecom

文件：569.4 Kbytes 页数：24 Pages

TI

德州仪器