SHARC Dual-Core DSP with Arm Cortex-A5

SYSTEM FEATURES Dual-enhanced SHARC+ floating-point cores High performance SHARC+ cores (up to 1 GHz each) Up to 5 Mb (640 kB) L1 SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed-point support Byte, shor

文件：3.80618 Mbytes 页数：145 Pages

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SHARC Dual-Core DSP with Arm Cortex-A5

文件：3.26181 Mbytes 页数：143 Pages

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高达1 GHz的双核SHARC+® DSP，集成Arm® Cortex®-A5

ADSP-SC59x处理器运行速度可达1 GHz，属于SHARC®系列产品。 ADSP-SC59x 处理器是一款双核SHARC+® DSP，其音频性能为前代单核SHARC+ ADSP-2156x产品的两倍，并集成了Arm Cortex-A5内核，运行频率高达1 GHz。具有FPU和Neon® DSP扩展的A5处理器，可处理更多实时处理任务并管理音频应用中用于时效数据接口的外设。这些接口包括千兆以太网、USB高速、CAN FD和各种其他连接选项，用于灵活和简化的系统设计。\n\n ADSP-SC59x 处理器属于SIMD SHARC系列数字信号处理器(DSP)，采用ADI公司的Supe SHARC+内核基础架构 \n• 800 MHz（最大值）或1 GHz（最大值） 内核时钟频率\n\n• 2个640KB 片内1级(L1) SRAM存储器（支持奇偶校验）提高了低延迟性能\n\n• 支持32、40和64位浮点\n\n• 32位定点\n\n• 字节、短字、字、长字寻址\n\n\nArm内核基础架构： \n• 1 GHz Arm Cortex-A5（具有Neon/FPU）\n\n• 32kB/32kB L1指令/数据缓存\n\n• 256kB L2缓存\n\n\n存储器 \n• 2048 KB 片内2级(L2) SRAM，具有ECC保护功能，在许多用例中无需外部存储器\n\n• 针;

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SHARC Dual-Core DSP with Arm Cortex-A5

SYSTEM FEATURES Dual-enhanced SHARC+ floating-point cores High performance SHARC+ cores (up to 1 GHz each) Up to 5 Mb (640 kB) L1 SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed-point support Byte, shor

文件：3.80618 Mbytes 页数：145 Pages

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SHARC Dual-Core DSP with Arm Cortex-A5

SYSTEM FEATURES Dual-enhanced SHARC+ floating-point cores High performance SHARC+ cores (up to 1 GHz each) Up to 5 Mb (640 kB) L1 SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed-point support Byte, shor

文件：3.80618 Mbytes 页数：145 Pages

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SHARC Dual-Core DSP with Arm Cortex-A5

SYSTEM FEATURES Dual-enhanced SHARC+ floating-point cores High performance SHARC+ cores (up to 1 GHz each) Up to 5 Mb (640 kB) L1 SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed-point support Byte, shor

文件：3.80618 Mbytes 页数：145 Pages

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SHARC Dual-Core DSP with Arm Cortex-A5

SYSTEM FEATURES Dual-enhanced SHARC+ floating-point cores High performance SHARC+ cores (up to 1 GHz each) Up to 5 Mb (640 kB) L1 SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed-point support Byte, shor

文件：3.80618 Mbytes 页数：145 Pages

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SHARC Dual-Core DSP with Arm Cortex-A5

SYSTEM FEATURES Dual-enhanced SHARC+ floating-point cores High performance SHARC+ cores (up to 1 GHz each) Up to 5 Mb (640 kB) L1 SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed-point support Byte, shor

文件：3.80618 Mbytes 页数：145 Pages

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SHARC Dual-Core DSP with Arm Cortex-A5

SYSTEM FEATURES Dual-enhanced SHARC+ floating-point cores High performance SHARC+ cores (up to 1 GHz each) Up to 5 Mb (640 kB) L1 SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed-point support Byte, shor

文件：3.80618 Mbytes 页数：145 Pages

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SHARC Dual-Core DSP with Arm Cortex-A5

SYSTEM FEATURES Dual-enhanced SHARC+ floating-point cores High performance SHARC+ cores (up to 1 GHz each) Up to 5 Mb (640 kB) L1 SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed-point support Byte, shor

文件：3.80618 Mbytes 页数：145 Pages

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