ADS8902BRGER.B中文资料德州仪器数据手册PDF规格书

1 Features

1• Resolution: 20-Bits

• High Sample Rate With No Latency Output:

– ADS8900B: 1-MSPS

– ADS8902B: 500-kSPS

– ADS8904B: 250-kSPS

• Integrated LDO Enables Low-Power, Single-

Supply Operation

• Low Power Reference Buffer with No Droop

• Excellent AC and DC Performance:

– SNR: 104.5-dB, THD: –125-dB

– DNL: ±0.2-ppm, 20-Bit No-Missing-Codes

– INL: ±1-ppm

• Wide Input Range:

– Unipolar Differential Input Range: ±VREF

– VREF Input Range: 2.5-V to 5-V

• Enhanced-SPI Digital Interface

– Interface SCLK : 22-MHz at 1-MSPS.

– Configurable Data Parity Output.

• Extended Temperature Range: –40°C to +125°C

• Small Footprint: 4-mm × 4-mm VQFN

2 Applications

• Test and Measurement

• Medical Imaging

• High-Precision, High-Speed Data Acquisition

3 Description

The ADS8900B, ADS8902B, and ADS8904B

(ADS890xB) belong to a family of pin-to-pin

compatible, high-speed, single-channel, highprecision,

20-bit successive-approximation-register

(SAR) analog-to-digital converters (ADCs) with an

integrated reference buffer and integrated lowdropout

regulator (LDO). The device family includes

the ADS891xB (18-bit) and ADS892xB (16-bit)

resolution variants.

The ADS89xxB boosts analog performance while

maintaining high-resolution data transfer by using TI’s

Enhanced-SPI feature. Enhanced-SPI enables

ADS89xxB in achieving high throughput at lower

clock speeds, there by simplifying the board layout

and lowering system cost. Enhanced-SPI also

simplifies the host’s clocking-in of data there by

making it ideal for applications involving FPGAs,

DSPs. ADS89xxB is compatible with standard SPI

Interface.

The ADS89xxB has an internal data parity feature

which can be appended to the ADC data output. ADC

data validation by the host, using parity bits, improves

system reliability.