ADS61B23中文资料12 位、80MSPS 模数转换器 (ADC)数据手册TI规格书

描述 Description

ADS61B23 is a 12-bit A/D converter (ADC) with a maximum sampling frequency of 80 MSPS. It combines high performance and low power consumption in a compact 32-QFN package. The analog inputs use buffers to isolate the switching transients of the internal sample & hold from the external driving circuit. The buffered inputs present very low input capacitance (< 2pF) & wide bandwidth. This makes it easy to drive them at high input frequencies, compared to an ADC without the input buffers.ADS61B23 has coarse and fine gain options that are used to improve SFDR performance at lower full-scale analog input ranges.The digital data outputs are parallel CMOS or DDR LVDS (Double Data Rate). Several features exist to ease data capture—controls for output clock position and output buffer drive strength, plus LVDS current and internal termination programmability. The output interface type, gain, and other functions are programmed using a 3-wire serial interface. Alternatively, some of these functions are configured using dedicated parallel pins so the device starts in the desired state after power-up. ADS61B23 includes internal references, while eliminating the traditional reference pins and associated external decoupling. External reference mode is also supported.

ADS61B23 is a 12-bit A/D converter (ADC) with a maximum sampling frequency of 80 MSPS. It combines high performance and low power consumption in a compact 32-QFN package. The analog inputs use buffers to isolate the switching transients of the internal sample & hold from the external driving circuit. The buffered inputs present very low input capacitance (< 2pF) & wide bandwidth. This makes it easy to drive them at high input frequencies, compared to an ADC without the input buffers.ADS61B23 has coarse and fine gain options that are used to improve SFDR performance at lower full-scale analog input ranges.The digital data outputs are parallel CMOS or DDR LVDS (Double Data Rate). Several features exist to ease data capture—controls for output clock position and output buffer drive strength, plus LVDS current and internal termination programmability. The output interface type, gain, and other functions are programmed using a 3-wire serial interface. Alternatively, some of these functions are configured using dedicated parallel pins so the device starts in the desired state after power-up. ADS61B23 includes internal references, while eliminating the traditional reference pins and associated external decoupling. External reference mode is also supported.

特性 Features

• Maximum Sample Rate: 80 MSPS
• Buffered Analog Inputs with
• 82 dBc SFDR and 70 dBFS SNR(-1 BFS or 1.8 Vpp input)
• 3.5 dB Coarse Gain and up to 6 dB Programmable Fine Gain for SNR and SFDR Trade-Off
• Supports Sine, LVCMOS, LVPECL, LVDS Clock Inputs and Clock Amplitude Down to 400 mVPP
• Internal Reference with Support for External Reference
• Programmable Output Clock Position and Drive Strength to Ease Data Capture
• 32-pin QFN Package (5 mm × 5 mm)
• Temperature range -40°C to 85°C
• Wireless Communications Infrastructure
• Power Amplifier Linearization
• Test and Measurement Instrumentation
• Medical Imaging
• Radar Systems