ADRV9044数据手册ADI中文资料规格书

描述 Description

The ADRV9044 is a highly integrated, system on chip (SoC) RF agile transceiver with integrated digital front end (DFE). The SoC contains four transmitters, two observation receivers to monitor transmitter channels, four receivers, integrated LO and clock synthesizers, and digital signal processing functions. The SoC meets the high radio performance and low power consumption demanded by cellular infrastructure applications including small cell base-station radios, macro 3G/4G/5G systems, and massive MIMO base stations.\r
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The receiver and transmitter signal paths use a zero-IF (ZIF) architecture that provides wide bandwidth with dynamic range suitable for contiguous and non-contiguous multi-carrier base-station applications. The ZIF architecture has the benefits of low power plus RF frequency and bandwidth agility. The lack of aliases and out-of-band images eliminate anti-aliasing and image filters. This reduces both system size and cost, also making band independent solutions possible.\r
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The device also includes two wide-bandwidth observation path receiver subsystems to monitor transmitter outputs. This SoC subsystem includes automatic and manual attenuation control, DC offset correction, quadrature error correction (QEC), and digital filtering. GPIOs that provide an array of digital control options are also integrated.\r
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Multi-band capability is enabled by additional LO dividers and wideband operation. This allows two individuals band profiles within the tunable range, so maximizing use case flexibility.\r
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The SoC has fully integrated DFE functionality, which includes carrier digital up/down conversion (CDUC and CDDC), crest factor reduction (CFR), digital predistortion (DPD), closed-loop gain control (CLGC) and voltage standing wave ratio (VSWR) monitor.\r
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The CDUC feature of the ADRV9044 filters and places individual component carriers within the band of interest. The CDDC feature, with its eight parallel paths, processes each carrier individually before sending over the serial data interface.\r
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The CDUC and CDDC reduce serialization/deserialization (SERDES) interface data rates in non-contiguous carrier configurations. This integration also reduces power compared to an equivalent FPGA based implementation.\r
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The CFR engine of the ADRV9044 reduces the peak-to-average ratio (PAR) of the input signal, which enables higher efficiency transmit line ups while reducing the processing load on baseband processors.\r
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The SoC also contains a fully integrated DPD engine for use in power amplifier linearization. The DPD enables the high-efficiency power amplifiers, which reduce the power consumption of base-station radios and the number of SERDES lanes interfacing with baseband processors. The DPD engine incorporates a dedicated long-term DPD (LT-DPD) block, which provides the support for GaN power amplifiers. The ADRV9044 tackles charge-trapping property of GaN power amplifiers with its LT-DPD block, hence improving the emissions and error vector magnitude (EVM). The SoC includes an ARM Cortex-A55 quad core processor to independently serve DPD, CLGC, and VSWR monitor features. The dedicated processor, together with the DPD engine, provides industry leading DPD performance.\r
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The serial data interface consists of eight serializer and deserializer lanes. The interface supports the JESD204C standards, and both fixed and floating-point data formats are supported. The floatingpoint format allows internal automatic gain control (AGC) to be transparent to the baseband processor.\r
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The ADRV9044 is powered directly from 0.8 V, 1.0 V, and 1.8 V regulators and is controlled through a standard SPI serial port. The comprehensive power-down modes are included to minimize the power consumption in normal use. The device is packaged in a 27 mm × 20 mm, 736-ball grid array.

特性 Features

• Four differential transmitters (Tx)\r
• Four differential receivers (Rx)\r
• Two differential observation receivers (ORx)\r
• Tunable range: 600 MHz to 6000 MHz\r
• Single-band and multiband (N x 2T2R/4T4R) capability\r
• Four individual band profiles within tunable range (band profiles define bandwidth and aggregate sampling rate of a channel)\r
• ADRV9044BBPZ-WB supports DPD for 400 MHz iBW/OBW\r
• Simplifying system thermal solution\r
• Power consumption-optimized DFE engines\r
• 125°C maximum junction temperature for intermittent operation, 110°C for continuous (operating lifetime impact at >110°C can be offset by operation at <110°C based on acceleration factors)\r
• Fully integrated DFE (DPD, CDUC, CDDC, and CFR) engine that reduces FPGAs resources and halves SERDES lane rate\r
• DPD adaptation engine for power amplifier linearization\r
• CDUC/CDDC—maximum eight component carriers (CCs) per each transmitter/receiver channel\r
• Multistage CFR engine\r
• Supports DTx (micro sleep) power saving mode in downlink\r
• Supports JESD204B and JESD204C digital interface\r
• Multichip phase synchronization for all local oscillator (LO) and baseband clocks\r
• Dual fully integrated fractional-N RF synthesizers\r
• Fully integrated clock synthesizer