ADRV9005数据手册ADI中文资料规格书

描述 Description

The ADRV9005 is a highly integrated RF transceiver that hasintegrated synthesizers and digital signal processing functions.
The ADRV9005 is a high performance, highly linear, high dynamicrange transceiver designed for performance vs. power consumptionsystem optimization. The device is configurable and ideally suitedto demanding, low power, portable and battery powered equipment.The ADRV9005 operates from 30 MHz to 6000 MHz and covers theUHF, VHF, industrial, scientific, and medical (ISM) bands, and cellularfrequency bands in narrow-band (kHz) and wideband operationup to 40 MHz.
The transceiver consists of direct conversion signal paths withstate-of-the-art noise figure and linearity. Each complete receiverand transmitter subsystem includes dc offset correction, quadratureerror correction (QEC), and programmable digital filters, whicheliminate the need for these functions in the digital baseband. In addition,several auxiliary functions, such as auxiliary analog-to-digitalconverters (ADCs), auxiliary digital-to-analog converters (DACs),and general-purpose inputs/outputs (GPIOs), are integrated to provideadditional monitoring and control capability.
The fully integrated phase-locked loops (PLLs) provide high performance,low power, fractional-N frequency synthesis for the transmitter,receiver, and clock sections. Careful design and layout techniquesprovide the isolation required in high performance personalradio applications.
All voltage controlled oscillator (VCO) and loop filter componentsare integrated to minimize the external component count. The localoscillators (LOs) have flexible configuration options and include fastlock modes.
The transceiver includes low power sleep and monitor modes tosave power and extend the battery life of portable devices whilemonitoring communications.The fully integrated, low power digital predistortion (DPD) is optimizedfor both narrow-band and wideband signals and enableslinearization of high efficiency power amplifiers.
The ADRV9005 core can be powered directly from 1.0 V, 1.3 V,and 1.8 V regulators and is controlled via a standard 4-wire serialport. Other voltage supplies are used to provide proper digital interfacelevels and to optimize the receiver, transmitter, and auxiliaryconverter performance.
High data rate and low data rate interfaces are supported usingconfigurable CMOS or low voltage differential signaling (LVDS)serial synchronous interface (SSI) choice.
The ADRV9005 is packaged in a 12 mm × 12 mm, 196-ball chipscale package ball grid array (CSP_BGA).
APPLICATIONS

Mission critical communications Very high frequency (VHF), ultrahigh frequency (UHF), and cellular to 6 GHz Time division duplexing (TDD)

特性 Features

1 × 1 highly integrated transceiver Frequency range of 30 MHz to 6000 MHz Transmitter and receiver bandwidth from 12 kHz to 40 MHz Two fully integrated, fractional-N, RF synthesizers LVDS and CMOS synchronous serial data interface options Low power monitor and sleep modes Multichip synchronization capabilities Fast frequency hopping Dynamic profile switching for dynamic data rates and sample ratesFully integrated DPD for narrow-band and wideband waveforms Fully programmable via a 4-wire SPI 12 mm × 12 mm, 196-ball CSP_BGA