Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp

GENERAL DESCRIPTION The ADN2812 provides the receiver functions of quantization, signal level detect, and clock and data recovery for continuous data rates from 12.3 Mb/s to 2.7 Gb/s. The ADN2812 automatically locks to all data rates without the need for an external reference clock or programming

文件：478.05 Kbytes 页数：28 Pages

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亚德诺

Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp

FEATURES Serial data input: 12.3 Mb/s to 2.7 Gb/s Exceeds SONET requirements for jitter transfer/ generation/tolerance Quantizer sensitivity: 6 mV typical Adjustable slice level: ±100 mV Patented clock recovery architecture Loss of signal (LOS) detect range: 3 mV to 15 mV Independent slice

文件：409.25 Kbytes 页数：28 Pages

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连续速率12.3 Mb/s至2.7 Gb/s时钟和数据恢复IC，集成限幅放大器

ADN2812可提供下列接收器功能：量化、信号电平检测、时钟和数据恢复，适用于从12.3 Mb/s到2.7 Gb/s的连续数据速率。它可自动锁定至所有数据速率，而无需外部参考时钟或编程。该器件满足所有的SONET抖动要求，包括抖动传递、抖动产生和抖动容差。所有规格均相对于−40°C至+85°C环境温度而言，除非另有说明。                                      \n\n 该器件配合PIN二极管和TIA前置放大器，可以实现高度集成的低成本、低功耗光纤接收器。\n\n 当输入信号电平降至用户可调阈值以下时，接收器前端信号丢失(LOS)检测电路会 • 串行数据输入：12.3 Mb/s至2.7 Gb/s\n\n• 超过SONET抖动传递/产生/容差要求\n\n• 量化器灵敏度：6 mV（典型值）\n\n• 可调限幅电平：±100 mV\n\n• 取得专利的时钟恢复架构\n\n• 信号丢失(LOS)检测范围：3 mV至15 mV\n\n• 独立限幅电平调整和LOS检测器\n\n• 无需参考时钟\n\n• 失锁指示器\n\n• 通过I2C 接口访问可选特性\n\n• 单电源供电：3.3 V\n\n• 低功耗：750 mW（典型值）;

ADI

亚德诺

Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp

FEATURES Serial data input: 12.3 Mb/s to 2.7 Gb/s Exceeds SONET requirements for jitter transfer/ generation/tolerance Quantizer sensitivity: 6 mV typical Adjustable slice level: ±100 mV Patented clock recovery architecture Loss of signal (LOS) detect range: 3 mV to 15 mV Independent slice

文件：409.25 Kbytes 页数：28 Pages

AD

亚德诺

Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp

GENERAL DESCRIPTION The ADN2812 provides the receiver functions of quantization, signal level detect, and clock and data recovery for continuous data rates from 12.3 Mb/s to 2.7 Gb/s. The ADN2812 automatically locks to all data rates without the need for an external reference clock or programming

文件：478.05 Kbytes 页数：28 Pages

AD

亚德诺

Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp

GENERAL DESCRIPTION The ADN2812 provides the receiver functions of quantization, signal level detect, and clock and data recovery for continuous data rates from 12.3 Mb/s to 2.7 Gb/s. The ADN2812 automatically locks to all data rates without the need for an external reference clock or programming

文件：478.05 Kbytes 页数：28 Pages

AD

亚德诺

Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp

GENERAL DESCRIPTION The ADN2812 provides the receiver functions of quantization, signal level detect, and clock and data recovery for continuous data rates from 12.3 Mb/s to 2.7 Gb/s. The ADN2812 automatically locks to all data rates without the need for an external reference clock or programming

文件：478.05 Kbytes 页数：28 Pages

AD

亚德诺

Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and Data Recovery

GENERAL DESCRIPTION The ADN2812 provides the receiver functions of quantization, signal level detect, and clock and data recovery for continuous data rates from 12.3 Mb/s to 2.7 Gb/s. The ADN2812 automatically locks to all data rates without the need for an external reference clock or programming

文件：409.83 Kbytes 页数：28 Pages

AD

亚德诺

Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp

FEATURES Serial data input: 12.3 Mb/s to 2.7 Gb/s Exceeds SONET requirements for jitter transfer/ generation/tolerance Quantizer sensitivity: 6 mV typical Adjustable slice level: ±100 mV Patented clock recovery architecture Loss of signal (LOS) detect range: 3 mV to 15 mV Independent slice

文件：409.25 Kbytes 页数：28 Pages

AD

亚德诺

Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp

FEATURES Serial data input: 12.3 Mb/s to 2.7 Gb/s Exceeds SONET requirements for jitter transfer/ generation/tolerance Quantizer sensitivity: 6 mV typical Adjustable slice level: ±100 mV Patented clock recovery architecture Loss of signal (LOS) detect range: 3 mV to 15 mV Independent slice

文件：409.25 Kbytes 页数：28 Pages

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亚德诺