ADN2812_V01中文资料亚德诺数据手册PDF规格书

厂商型号	ADN2812_V01
功能描述	Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp
文件大小	409.25 Kbytes
页面数量	28 页
生产厂商	AD
中文名称	亚德诺
网址	网址
数据手册	下载地址一下载地址二到原厂下载
更新时间	2025-10-4 15:01:00
人工找货	ADN2812_V01价格和库存，欢迎联系客服免费人工找货

FEATURES

Serial data input: 12.3 Mb/s to 2.7 Gb/s

Exceeds SONET requirements for jitter transfer/ generation/tolerance

Quantizer sensitivity: 6 mV typical

Adjustable slice level: ±100 mV

Patented clock recovery architecture

Loss of signal (LOS) detect range: 3 mV to 15 mV

Independent slice level adjust and LOS detector

No reference clock required

Loss of lock indicator

I2C interface to access optional features

Single-supply operation: 3.3 V

Low power: 750 mW typical

5 mm × 5 mm 32-lead LFCSP

APPLICATIONS

SONET OC-1/OC-3/OC-12/OC-48 and all associated FEC rates

Fibre Channel, 2× Fibre Channel, GbE, HDTV

WDM transponders

Regenerators/repeaters

Test equipment

Broadband cross-connects and routers