1.8 V, 6 LVDS/12 CMOS Outputs Low Power Clock Fanout Buffer

CIRCUIT DESCRIPTION The circuit in Figure 1 was constructed by connecting the respective evaluation boards for the individual products. Connections were made with matched cable lengths. The first of three basic requirements to synchronize multiple AD9910’s is to provide a co-incident reference

文件：524.01 Kbytes 页数：16 Pages

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Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers

CIRCUIT DESCRIPTION The circuit in Figure 1 was constructed by connecting the respective evaluation boards for the individual products. Connections were made with matched cable lengths. The first of three basic requirements to synchronize multiple AD9910’s is to provide a co-incident reference

文件：390.99 Kbytes 页数：3 Pages

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1.8 V, 6 LVDS/12 CMOS Outputs Low Power Clock Fanout Buffer

文件：468.98 Kbytes 页数：15 Pages

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1.8 V、6 LVDS/12 CMOS输出低功耗时钟扇出缓冲器

ADCLK846是一款针对低抖动和低功耗优化的1.2 GHz/250 MHz、LVDS/CMOS、扇出缓冲器。可配置范围为6 LVDS至12 CMOS输出，包括LVDS和CMOS输出的组合。两条控制线路用于确定固定模块输出是LVDS输出还是CMOS输出。\n\n 时钟输入接受各种单端和差分逻辑电平，包括LVPECL、LVDS、HSTL、CML和CMOS。\n\n 表8提供用于各类连接的接口选项。SLEEP引脚使能睡眼模式以关断器件的电源。\n\n 这款器件采用24引脚LFCSP封装，工作温度范围为−40℃至+85℃的标准工业温度范围。 • 可选LVDS/CMOS输出\n\n• 多达6 LVDS（1.2 GHz）或者12 CMOS（250 MHz）输出\n\n• 每通道功耗：<16 mW（工作频率为100 MHz）\n\n• 综合抖动：54 fs（12 kHz至20 MHz）\n\n• 附加宽带抖动：100 fs;

ADI

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1.8 V, 6 LVDS/12 CMOS Outputs Low Power Clock Fanout Buffer

CIRCUIT DESCRIPTION The circuit in Figure 1 was constructed by connecting the respective evaluation boards for the individual products. Connections were made with matched cable lengths. The first of three basic requirements to synchronize multiple AD9910’s is to provide a co-incident reference

文件：524.01 Kbytes 页数：16 Pages

AD

亚德诺

1.8 V, 6 LVDS/12 CMOS Outputs Low Power Clock Fanout Buffer

CIRCUIT DESCRIPTION The circuit in Figure 1 was constructed by connecting the respective evaluation boards for the individual products. Connections were made with matched cable lengths. The first of three basic requirements to synchronize multiple AD9910’s is to provide a co-incident reference

文件：524.01 Kbytes 页数：16 Pages

AD

亚德诺

1.8 V, 6 LVDS/12 CMOS Outputs Low Power Clock Fanout Buffer

CIRCUIT DESCRIPTION The circuit in Figure 1 was constructed by connecting the respective evaluation boards for the individual products. Connections were made with matched cable lengths. The first of three basic requirements to synchronize multiple AD9910’s is to provide a co-incident reference

文件：524.01 Kbytes 页数：16 Pages

AD

亚德诺

1.8 V, 6 LVDS/12 CMOS Outputs Low Power Clock Fanout Buffer

CIRCUIT DESCRIPTION The circuit in Figure 1 was constructed by connecting the respective evaluation boards for the individual products. Connections were made with matched cable lengths. The first of three basic requirements to synchronize multiple AD9910’s is to provide a co-incident reference

文件：524.01 Kbytes 页数：16 Pages

AD

亚德诺

1.8 V, 6 LVDS/12 CMOS Outputs Low Power Clock Fanout Buffer

文件：468.98 Kbytes 页数：15 Pages

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1.8 V, 6 LVDS/12 CMOS Outputs Low Power Clock Fanout Buffer

文件：468.98 Kbytes 页数：15 Pages

AD

亚德诺