ADC3664-SP中文资料耐辐射保障 (RHA)、QMLV、300krad、14 位、双通道、125MSPS ADC数据手册TI规格书

描述 Description

The ADC3664-SP is a low latency, low noise, and ultra low power, 14-bit, 125MSPS, high-speed dual channel ADC. Designed for best noise performance, the device delivers a noise spectral density of –156.9dBFS/Hz combined with excellent linearity and dynamic range. The ADC3664-SP offers DC precision together with IF sampling support to enable the design of a wide range of applications. The low latency architecture (as low as 1 clock cycle latency) and high sample rate also enable high speed control loops. The ADC consumes only 100mW/ch at 125MSPS and the power consumption scales well with sampling rate.

The device uses a serial LVDS (SLVDS) interface to output the data which minimizes the number of digital interconnects. The device also integrates a digital down converter (DDC) to help reduce the data rate and lower system power consumption. The device is pin-to-pin compatible with the 18-bit, 65MSPS ADC3683-SP. It comes in a 64-pin CFP package (10.9mm x 10.9mm) and supports a temperature range from –55°C to +105°C.

特性 Features

Screening and radiation performance

QMLV screening and reliability assurance

Total ionizing dose (TID): 300krad (Si)

Single event latch-up (SEL): 75MeV-cm2/mg



Ambient temperature range: -55°C to 105°C

Dual Channel ADC

14-bit 125MSPS

Noise floor: -156.9dBFS/Hz

Low power consumption: 100mW/ch

Latency: 2 clock cycles

Clock rate versus voltage reference:

External reference: 1MSPS to 125MSPS

Internal reference: 100MSPS to 125MSPS



14-Bit, no missing codes

Input bandwidth: 200MHz (-3dB)

INL: ±2.6LSB; DNL: ±0.9LSB

Optional digital down converter (DDC):

Real or complex decimation

Decimation by 2, 4, 8, 16, and 32

32-bit NCO



Serial LVDS (SLVDS) interface (2-, 1-, and 1/2-wire)

Spectral performance (FIN = 5MHz):

SNR: 77.5dBFS

SFDR: 84dBc HD2, HD3

Non HD23: 91dBc