ADC3564数据手册TI中文资料规格书

描述 Description

The ADC3564 device is a low-noise, ultra-low power, 14-bit, 125-MSPS, high-speed ADC. Designed for low power consumption, the device delivers a noise spectral density of –156 dBFS/Hz combined with excellent linearity and dynamic range. The ADC3564 offers IF sampling support which makes the device suited for a wide range of applications. High-speed control loops benefit from the short latency of as little as one clock cycle. The ADC consumes only 137 mW at 125 MSPS, and the power consumption scales well with lower sampling rates.

The ADC3564 uses serial LVDS (SLVDS) interface to output the data which minimizes the number of digital interconnects. The device supports two-lane, one-lane and half-lane options. The device is a pin-to-pin compatible family with different speed grades and comes in a 40-pin VQFN package. The device supports the extended industrial temperature range from –40 to +105⁰C.

特性 Features

• 14-Bit 125 MSPS ADC
• Noise floor: –156 dBFS/Hz
• Ultra low power: 137 mW at 125 Msps
• Latency: ≤ 2 clock cycles
• Specified 14-bit, no missing codes
• INL: ±1.5 LSB; DNL: ±0.5 LSB
• Reference: external or internal
• Input bandwidth: 1200 MHz (3 dB)
• Industrial temperature range: –40°C to +105°C
• On-chip digital filter (optional)
• Decimation by 2, 4, 8, 16, 32
• 32-bit NCO

• Serial LVDS digital interface (2-, 1- and 1/2-wire)
• Small footprint: 40-WQFN (5 mm × 5 mm) package
• Spectral performance (fIN = 10 MHz):
• SNR: 77.5 dBFS
• SFDR: 80-dBc HD2, HD3
• SFDR: 95-dBFS worst spur

• Spectral performance (fIN = 70 MHz):
• SNR: 75 dBFS
• SFDR: 75-dBc HD2, HD3
• SFDR: 90-dBFS worst spur