Tiny, Low Power JFET-Input Op Amp

GENERAL DESCRIPTION The ADA4062-2 and ADA4062-4 are dual and quad JFET-input amplifiers with industry-leading performance. They offer lower power, offset voltage, drift, and ultralow bias current. The ADA4062-2 B grade (SOIC package) features a typical low offset voltage of 0.5 mV, an offset drif

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22 μA, RRIO, CMOS, 18 V Operational Amplifier

FEATURES Micropower at high voltage (18 V): 22 μA maximum Low input bias current: 20 pA maximum Gain bandwidth product: 240 kHz at AV =100 typical Unity-gain crossover: 240 kHz −3 dB closed-loop bandwidth: 310 kHz Slew rate: 80 V/ms Large signal voltage gain: 110 dB minimum Single-supply operat

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Low Power JFET-Input Op Amps

FEATURES Low input bias current: 50 pA maximum Offset voltage 1.5 mV maximum for B grade (ADA4062-2 SOIC package) 2.5 mV maximum for A grade Offset voltage drift: 5 μV/°C typical Slew rate: 3.3 V/μs typical CMRR: 90 dB typical Low supply current: 165 μA typical High input impedance Unity

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22 關A, RRIO, CMOS, 18 V

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微型、低功耗JFET输入运算放大器

ADA4062-2和ADA4062-4分别为具有业界领先性能的双通道和四通道JFET输入放大器。二者具有低功耗、低失调电压、低漂移和超低偏置电流特性。ADA4062-2 B级（SOIC封装）的典型失调电压低至0.5 mV，失调漂移为4 μV/°C，偏置电流为2 pA。\n\nADA4062系列适合许多应用，包括过程控制、工业和仪器仪表设备、有源滤波、数据转换、缓冲以及功率控制和监测。每个放大器的电源电流低至165 μA，因而这些器件非常适合低功耗应用。\n\n ADA4062系列的额定温度范围为−40°C至+125°C扩展工业温度范围。ADA4062-2提供8引脚SOIC、8引脚MS • 低输入偏置电流：50 pA（最大值）\n\n• 失调电压\n1.5 mV（最大值，ADA4062-2 B级）\n2.5 mV（最大值，ADA4062-2 A级）\n\n• 失调电压漂移：4 μV/°C（典型值）\n\n• 压摆率：3.3 V/μs（典型值）\n\n• 共模抑制比（CMRR）：90 dB（典型值）\n\n• 低电源电流：165μA（典型值）\n\n• 高输入阻抗\n\n• 单位增益稳定\n\n• 封装：SOIC、MSOP、LFCSP和TSSOP;

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Low Power JFET-Input Op Amps

FEATURES Low input bias current: 50 pA maximum Offset voltage 1.5 mV maximum for B grade (ADA4062-2 SOIC package) 2.5 mV maximum for A grade Offset voltage drift: 5 μV/°C typical Slew rate: 3.3 V/μs typical CMRR: 90 dB typical Low supply current: 165 μA typical High input impedance Unity

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丝印：J；Package：LFCSP_UQ；Low Power JFET-Input Op Amps

FEATURES Low input bias current: 50 pA maximum Offset voltage 1.5 mV maximum for B grade (ADA4062-2 SOIC package) 2.5 mV maximum for A grade Offset voltage drift: 5 μV/°C typical Slew rate: 3.3 V/μs typical CMRR: 90 dB typical Low supply current: 165 μA typical High input impedance Unity

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丝印：J；Package：LFCSP_UQ；Low Power JFET-Input Op Amps

FEATURES Low input bias current: 50 pA maximum Offset voltage 1.5 mV maximum for B grade (ADA4062-2 SOIC package) 2.5 mV maximum for A grade Offset voltage drift: 5 μV/°C typical Slew rate: 3.3 V/μs typical CMRR: 90 dB typical Low supply current: 165 μA typical High input impedance Unity

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丝印：J；Package：LFCSP_UQ；Low Power JFET-Input Op Amps

FEATURES Low input bias current: 50 pA maximum Offset voltage 1.5 mV maximum for B grade (ADA4062-2 SOIC package) 2.5 mV maximum for A grade Offset voltage drift: 5 μV/°C typical Slew rate: 3.3 V/μs typical CMRR: 90 dB typical Low supply current: 165 μA typical High input impedance Unity

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丝印：A25；Package：MSOP；Low Power JFET-Input Op Amps

FEATURES Low input bias current: 50 pA maximum Offset voltage 1.5 mV maximum for B grade (ADA4062-2 SOIC package) 2.5 mV maximum for A grade Offset voltage drift: 5 μV/°C typical Slew rate: 3.3 V/μs typical CMRR: 90 dB typical Low supply current: 165 μA typical High input impedance Unity

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