10-Bit, 105 MSPS/125 MSPS/150 MSPS,1.8 V Dual Analog-to-Digital Converter

FEATURES ► SNR = 60.6 dBc (61.6 dBFS) to 70 MHz at 150 MSPS ► SFDR = 81 dBc to 70 MHz at 150 MSPS ► Low power: 825 mW at 150 MSPS ► 1.8 V analog supply operation ► 1.8 V to 3.3 V CMOS output supply or 1.8 V LVDS supply ► Integer 1 to 8 input clock divider ► Intermediate frequency (IF) sampl

文件：6.82256 Mbytes 页数：72 Pages

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1.8 V Dual Analog-to-Digital Converter

文件：2.33584 Mbytes 页数：73 Pages

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10位、105 MSPS/125 MSPS/150 MSPS、1.8 V双核模数转换器

AD9600是一款双核、10位、105 MSPS/125 MSPS/150 MSPS ADC，旨在支持要求低成本、小尺寸和多功能特性的通信应用。 这款双核ADC采用多级、差分流水线架构，并集成了输出纠错逻辑。每个ADC均具有宽带宽、差分采样保持模拟输入放大器，支持用户可选的各种输入范围。集成基准电压源可简化设计。占空比稳定器可用来补偿ADC时钟占空比的波动，使转换器保持出色的性能。\n\n AD9600内置多种功能，可以简化通信接收机中的自动增益控制（AGC）功能。例如，快速检测特性可以通过输出四位输入电平信息实现快速检测超量程输入，并且延迟极短。此外，利用ADC的4个快速 • 信噪比（SNR）：60.6 dBc\n（61.6 dBFS，至70 MHz、150 MSPS）\n\n• 无杂散动态范围（SFDR）：\n81 dBc（至70 MHz、150 MSPS）\n\n• 低功耗：825 mW（150 MSPS）\n\n• 1.8 V模拟电源供电\n\n• 1.8 V至3.3 V CMOS输出电源或1.8 V LVDS电源\n\n• 1至8整数输入时钟除法器;

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10-Bit, 105 MSPS/125 MSPS/150 MSPS,1.8 V Dual Analog-to-Digital Converter

FEATURES ► SNR = 60.6 dBc (61.6 dBFS) to 70 MHz at 150 MSPS ► SFDR = 81 dBc to 70 MHz at 150 MSPS ► Low power: 825 mW at 150 MSPS ► 1.8 V analog supply operation ► 1.8 V to 3.3 V CMOS output supply or 1.8 V LVDS supply ► Integer 1 to 8 input clock divider ► Intermediate frequency (IF) sampl

文件：6.82256 Mbytes 页数：72 Pages

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亚德诺

10-Bit, 105 MSPS/125 MSPS/150 MSPS,1.8 V Dual Analog-to-Digital Converter

FEATURES ► SNR = 60.6 dBc (61.6 dBFS) to 70 MHz at 150 MSPS ► SFDR = 81 dBc to 70 MHz at 150 MSPS ► Low power: 825 mW at 150 MSPS ► 1.8 V analog supply operation ► 1.8 V to 3.3 V CMOS output supply or 1.8 V LVDS supply ► Integer 1 to 8 input clock divider ► Intermediate frequency (IF) sampl

文件：6.82256 Mbytes 页数：72 Pages

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亚德诺

10-Bit, 105 MSPS/125 MSPS/150 MSPS,1.8 V Dual Analog-to-Digital Converter

FEATURES ► SNR = 60.6 dBc (61.6 dBFS) to 70 MHz at 150 MSPS ► SFDR = 81 dBc to 70 MHz at 150 MSPS ► Low power: 825 mW at 150 MSPS ► 1.8 V analog supply operation ► 1.8 V to 3.3 V CMOS output supply or 1.8 V LVDS supply ► Integer 1 to 8 input clock divider ► Intermediate frequency (IF) sampl

文件：6.82256 Mbytes 页数：72 Pages

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亚德诺

10-Bit, 105 MSPS/125 MSPS/150 MSPS,1.8 V Dual Analog-to-Digital Converter

FEATURES ► SNR = 60.6 dBc (61.6 dBFS) to 70 MHz at 150 MSPS ► SFDR = 81 dBc to 70 MHz at 150 MSPS ► Low power: 825 mW at 150 MSPS ► 1.8 V analog supply operation ► 1.8 V to 3.3 V CMOS output supply or 1.8 V LVDS supply ► Integer 1 to 8 input clock divider ► Intermediate frequency (IF) sampl

文件：6.82256 Mbytes 页数：72 Pages

AD

亚德诺

10-Bit, 105 MSPS/125 MSPS/150 MSPS,1.8 V Dual Analog-to-Digital Converter

FEATURES ► SNR = 60.6 dBc (61.6 dBFS) to 70 MHz at 150 MSPS ► SFDR = 81 dBc to 70 MHz at 150 MSPS ► Low power: 825 mW at 150 MSPS ► 1.8 V analog supply operation ► 1.8 V to 3.3 V CMOS output supply or 1.8 V LVDS supply ► Integer 1 to 8 input clock divider ► Intermediate frequency (IF) sampl

文件：6.82256 Mbytes 页数：72 Pages

AD

亚德诺

10-Bit, 105 MSPS/125 MSPS/150 MSPS,1.8 V Dual Analog-to-Digital Converter

FEATURES ► SNR = 60.6 dBc (61.6 dBFS) to 70 MHz at 150 MSPS ► SFDR = 81 dBc to 70 MHz at 150 MSPS ► Low power: 825 mW at 150 MSPS ► 1.8 V analog supply operation ► 1.8 V to 3.3 V CMOS output supply or 1.8 V LVDS supply ► Integer 1 to 8 input clock divider ► Intermediate frequency (IF) sampl

文件：6.82256 Mbytes 页数：72 Pages

AD

亚德诺

10-Bit, 105 MSPS/125 MSPS/150 MSPS,1.8 V Dual Analog-to-Digital Converter

FEATURES ► SNR = 60.6 dBc (61.6 dBFS) to 70 MHz at 150 MSPS ► SFDR = 81 dBc to 70 MHz at 150 MSPS ► Low power: 825 mW at 150 MSPS ► 1.8 V analog supply operation ► 1.8 V to 3.3 V CMOS output supply or 1.8 V LVDS supply ► Integer 1 to 8 input clock divider ► Intermediate frequency (IF) sampl

文件：6.82256 Mbytes 页数：72 Pages

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