AD9600_V01中文资料亚德诺数据手册PDF规格书

FEATURES

► SNR = 60.6 dBc (61.6 dBFS) to 70 MHz at 150 MSPS

► SFDR = 81 dBc to 70 MHz at 150 MSPS

► Low power: 825 mW at 150 MSPS

► 1.8 V analog supply operation

► 1.8 V to 3.3 V CMOS output supply or 1.8 V LVDS supply

► Integer 1 to 8 input clock divider

► Intermediate frequency (IF) sampling frequencies up to 450 MHz

► Internal analog-to-digital converter (ADC) voltage reference

► Integrated ADC sample-and-hold inputs

► Flexible analog input: 1 V p-p to 2 V p-p range

► Differential analog inputs with 650 MHz bandwidth

► ADC clock duty cycle stabilizer

► 95 dB channel isolation/crosstalk

► Serial port control

► User-configurable built-in self-test (BIST) capability

► Energy-saving power-down modes

► Integrated receive features

► Fast detect/threshold bits

► Composite signal monitor

APPLICATIONS

► Point-to-point radio receivers (GPSK, QAM)

► Diversity radio systems

► I/Q demodulation systems

► Smart antenna systems

► Digital predistortion

► General-purpose software radios

► Broadband data applications

► Data acquisition

► Nondestructive testing