Fiber Channel/Ethernet Clock Generator IC, PLL Core, Dividers, 7 Clock Outputs

GENERAL DESCRIPTION The AD9572 provides a multioutput clock generator function along with two on-chip PLL cores, optimized for fiber channel line card applications that include an Ethernet interface. The integer-N PLL design is based on the Analog Devices, Inc., proven portfolio of high performan

文件：421.72 Kbytes 页数：20 Pages

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光纤通道/以太网时钟发生器IC，PLL内核，分频器，7路时钟输出

AD9572是一款多输出时钟发生器，具有两个片内PLL内核，针对包括以太网接口的光纤通道线路卡应用进行了优化。整数N分频PLL设计基于ADI公司成熟的高性能、低抖动频率合成器系列，可实现网络的较高性能。这款器件也适合相位噪声和抖动要求严格的其它应用。 PLL部分由低噪声鉴频鉴相器(PFD)、精密电荷泵(CP)、低相位噪声压控振荡器(VCO)、预编程的反馈分频器和输出分频器组成。通过将一个外部晶振或参考时钟连接到REFCLK引脚，可以将最高156.25 MHz的频率锁定至输入参考。每个输出分频比和反馈分频比针对所要求的输出速率进行预编程。 \n\n 第二个PLL也用作整数N分 • 完全集成的双VCO/PLL内核\n均方根抖动：167 fs（0.637 MHz至10 MHz，\n 106.25 MHz）\n均方根抖动：178 fs（1.875 MHz至20 MHz，\n 156.25 MHz） \n\n• 均方根抖动：418 fs（12 kHz至20 MHz，\n125 MHz输入晶振或25 MHz时钟频率）\n\n• 针对106.25 MHz、156.25 MHz、33.33 MHz、100 MHz、125 MHz提供预设分频比\n\n• 可选择LVPECL或LVDS输出格式\n\n• 集成环路滤波器\n\n\n\n• 参考时钟输出副本\n\n• 通过绑定引脚配置速;

ADI

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Fiber Channel/Ethernet Clock Generator IC, PLL Core, Dividers, 7 Clock Outputs

GENERAL DESCRIPTION The AD9572 provides a multioutput clock generator function along with two on-chip PLL cores, optimized for fiber channel line card applications that include an Ethernet interface. The integer-N PLL design is based on the Analog Devices, Inc., proven portfolio of high performan

文件：421.72 Kbytes 页数：20 Pages

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Fiber Channel/Ethernet Clock Generator IC, PLL Core, Dividers, 7 Clock Outputs

GENERAL DESCRIPTION The AD9572 provides a multioutput clock generator function along with two on-chip PLL cores, optimized for fiber channel line card applications that include an Ethernet interface. The integer-N PLL design is based on the Analog Devices, Inc., proven portfolio of high performan

文件：421.72 Kbytes 页数：20 Pages

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Fiber Channel/Ethernet Clock Generator IC, PLL Core, Dividers, 7 Clock Outputs

GENERAL DESCRIPTION The AD9572 provides a multioutput clock generator function along with two on-chip PLL cores, optimized for fiber channel line card applications that include an Ethernet interface. The integer-N PLL design is based on the Analog Devices, Inc., proven portfolio of high performan

文件：421.72 Kbytes 页数：20 Pages

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Fiber Channel/Ethernet Clock Generator IC, PLL Core, Dividers, 7 Clock Outputs

GENERAL DESCRIPTION The AD9572 provides a multioutput clock generator function along with two on-chip PLL cores, optimized for fiber channel line card applications that include an Ethernet interface. The integer-N PLL design is based on the Analog Devices, Inc., proven portfolio of high performan

文件：421.72 Kbytes 页数：20 Pages

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Fiber Channel/Ethernet Clock Generator IC, PLL Core, Dividers, 7 Clock Outputs

GENERAL DESCRIPTION The AD9572 provides a multioutput clock generator function along with two on-chip PLL cores, optimized for fiber channel line card applications that include an Ethernet interface. The integer-N PLL design is based on the Analog Devices, Inc., proven portfolio of high performan

文件：421.72 Kbytes 页数：20 Pages

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亚德诺

Fiber Channel/Ethernet Clock Generator IC, PLL Core, Dividers, 7 Clock Outputs

GENERAL DESCRIPTION The AD9572 provides a multioutput clock generator function along with two on-chip PLL cores, optimized for fiber channel line card applications that include an Ethernet interface. The integer-N PLL design is based on the Analog Devices, Inc., proven portfolio of high performan

文件：421.72 Kbytes 页数：20 Pages

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Fiber Channel/Ethernet Clock Generator IC, PLL Core, Dividers, 7 Clock Outputs

GENERAL DESCRIPTION The AD9572 provides a multioutput clock generator function along with two on-chip PLL cores, optimized for fiber channel line card applications that include an Ethernet interface. The integer-N PLL design is based on the Analog Devices, Inc., proven portfolio of high performan

文件：421.72 Kbytes 页数：20 Pages

AD

亚德诺

Fiber Channel/Ethernet Clock Generator IC, PLL Core, Dividers, 7 Clock Outputs

GENERAL DESCRIPTION The AD9572 provides a multioutput clock generator function along with two on-chip PLL cores, optimized for fiber channel line card applications that include an Ethernet interface. The integer-N PLL design is based on the Analog Devices, Inc., proven portfolio of high performan

文件：421.72 Kbytes 页数：20 Pages

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