丝印：ACT8990；Package：PLCC；TEST-BUS CONTROLLERS IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 16-BIT GENERIC HOST INTERFACES

Members of the Texas Instruments SCOPE E Family of Testability Products Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture Control Operation of Up to Six Parallel Target Scan Paths Accommodate Pipeline Delay to Target of Up to 31 Clock Cycl

文件：1.00942 Mbytes 页数：22 Pages

TI

德州仪器

丝印：ACT8990；Package：PLCC；TEST-BUS CONTROLLERS IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 16-BIT GENERIC HOST INTERFACES

Members of the Texas Instruments SCOPE E Family of Testability Products Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture Control Operation of Up to Six Parallel Target Scan Paths Accommodate Pipeline Delay to Target of Up to 31 Clock Cycl

文件：1.00942 Mbytes 页数：22 Pages

TI

德州仪器

丝印：ACT8990；Package：PLCC；TEST-BUS CONTROLLERS IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 16-BIT GENERIC HOST INTERFACES

Members of the Texas Instruments SCOPE E Family of Testability Products Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture Control Operation of Up to Six Parallel Target Scan Paths Accommodate Pipeline Delay to Target of Up to 31 Clock Cycl

文件：1.00942 Mbytes 页数：22 Pages

TI

德州仪器

丝印：ACT8990；Package：PLCC；TEST-BUS CONTROLLERS IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 16-BIT GENERIC HOST INTERFACES

Members of the Texas Instruments SCOPE E Family of Testability Products Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture Control Operation of Up to Six Parallel Target Scan Paths Accommodate Pipeline Delay to Target of Up to 31 Clock Cycl

文件：1.00942 Mbytes 页数：22 Pages

TI

德州仪器