AC Thyristor power switch

文件：232.94 Kbytes 页数：14 Pages

WEEN

瑞能半导体

AC Thyristor power switch

文件：233.63 Kbytes 页数：14 Pages

WEEN

瑞能半导体

AC Thyristor power switch

文件：1.38396 Mbytes 页数：14 Pages

WEEN

瑞能半导体

丝印：ACT109M；Package：SOIC；DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

Inputs Are TTL-Voltage Compatible Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption Balanced Propagation Delays ±24-mA Output Drive Current – Fanout to 15 F Devices SCR-Latchup-Resistant CMOS Process and Circuit Design Exceeds 2-kV ESD Protection Per MIL-STD-883,

文件：412.14 Kbytes 页数：14 Pages

TI

德州仪器

丝印：ACT109M；Package：SOIC；DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

Inputs Are TTL-Voltage Compatible Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption Balanced Propagation Delays ±24-mA Output Drive Current – Fanout to 15 F Devices SCR-Latchup-Resistant CMOS Process and Circuit Design Exceeds 2-kV ESD Protection Per MIL-STD-883,

文件：412.14 Kbytes 页数：14 Pages

TI

德州仪器

丝印：ACT109M；Package：SOIC；DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

Inputs Are TTL-Voltage Compatible Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption Balanced Propagation Delays ±24-mA Output Drive Current – Fanout to 15 F Devices SCR-Latchup-Resistant CMOS Process and Circuit Design Exceeds 2-kV ESD Protection Per MIL-STD-883,

文件：412.14 Kbytes 页数：14 Pages

TI

德州仪器

丝印：ACT10M；Package：SOIC；TRIPLE 3-INPUT POSITIVE-NAND GATES

Inputs Are TTL-Voltage Compatible Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption Balanced Propagation Delays ±24-mA Output Drive Current – Fanout to 15 F Devices SCR Latchup-Resistant CMOS Process and Circuit Design Exceeds 2-kV ESD Protection Per MIL-STD-883,

文件：462.81 Kbytes 页数：13 Pages

TI

德州仪器

丝印：ACT10M；Package：SOIC；TRIPLE 3-INPUT POSITIVE-NAND GATES

Inputs Are TTL-Voltage Compatible Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption Balanced Propagation Delays ±24-mA Output Drive Current – Fanout to 15 F Devices SCR Latchup-Resistant CMOS Process and Circuit Design Exceeds 2-kV ESD Protection Per MIL-STD-883,

文件：462.81 Kbytes 页数：13 Pages

TI

德州仪器

丝印：ACT10M；Package：SOIC；TRIPLE 3-INPUT POSITIVE-NAND GATES

Inputs Are TTL-Voltage Compatible Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption Balanced Propagation Delays ±24-mA Output Drive Current – Fanout to 15 F Devices SCR Latchup-Resistant CMOS Process and Circuit Design Exceeds 2-kV ESD Protection Per MIL-STD-883,

文件：462.81 Kbytes 页数：13 Pages

TI

德州仪器

丝印：ACT1071；Package：SOIC；10-BIT BUS-TERMINATION ARRAY WITH BUS-HOLD FUNCTION

Designed to Ensure Defined Voltage Levels on Floating Bus Lines in CMOS Systems Reduces Undershoot and Overshoot Caused By Line Reflections Repetitive Peak Forward Current . . . IFRM = 100 mA Inputs Are TTL-Voltage Compatible Low Power Consumption (Like CMOS) ESD Protection Exceeds 2000 V

文件：355.7 Kbytes 页数：11 Pages

TI

德州仪器