Jitter Attenuating, Multiplying Phase-Locked Loop with Automatic Input Switch and Data Resynchronization Path

Semtech

先之科

Jitter Attenuating, Multiplying Phase-Locked Loop with Automatic Input Switch and Data Resynchronization Path

文件：1.87998 Mbytes 页数：30 Pages

SEMTECH

先之科

Package：48-VFQFN 裸露焊盘；包装：卷带（TR） 类别：集成电路（IC） 应用特定时钟/定时 描述：IC JITTER ATT MULT PLL 48-QFN

SEMTECH

先之科

Dual P-Channel Enhancement Mode MOSFET

FEATURES ■ -30V, -4A, RDS(ON) = 65mΩ @VGS = -10V. RDS(ON) = 100mΩ @VGS = -4.5V. ■ Super high dense cell design for extremely low RDS(ON). ■ High power and current handing capability. ■ Surface mount Package.

文件：498.56 Kbytes 页数：5 Pages

CET

华瑞

Dual P-Channel Enhancement Mode Field Effect Transistor

文件：239.92 Kbytes 页数：5 Pages

FairchildFairchild Semiconductor

仙童半导体飞兆/仙童半导体公司

Dual P-Channel Enhancement Mode Field Effect Transistor

General Description These P-Channel enhancement mode power field effect transistors are produced using Fairchilds proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance and provide superior switching performance. Thes

文件：331.49 Kbytes 页数：10 Pages

FairchildFairchild Semiconductor

仙童半导体飞兆/仙童半导体公司