丝印：AB8；Package：SMB；600 W Transient Voltage Suppressor

1. General description 600 W uni- and bi-directional Transient Voltage Suppressor (TVS) in a SMB Surface-Mounted Device (SMD) plastic package, designed for transient voltage protection. 2. Features and benefits • Rated peak pulse power at 10/1000 μs waveform: PPPM = 600 W • Reverse standoff

文件：229.55 Kbytes 页数：12 Pages

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

丝印：AB823；Package：SSOP；9-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-IIBE BiCMOS Design Significantly Reduces Power Dissipation ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounc

文件：385.69 Kbytes 页数：16 Pages

TI2

德州仪器

丝印：AB823；Package：SSOP；9-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-IIBE BiCMOS Design Significantly Reduces Power Dissipation ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounc

文件：385.69 Kbytes 页数：16 Pages

TI2

德州仪器

丝印：AB823；Package：SSOP；9-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-IIBE BiCMOS Design Significantly Reduces Power Dissipation ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounc

文件：385.69 Kbytes 页数：16 Pages

TI2

德州仪器

丝印：AB827；Package：SSOP；10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

文件：519.58 Kbytes 页数：19 Pages

TI2

德州仪器

丝印：AB827；Package：SSOP；10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

文件：519.58 Kbytes 页数：19 Pages

TI2

德州仪器

丝印：AB827；Package：TSSOP；10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

文件：519.58 Kbytes 页数：19 Pages

TI2

德州仪器

丝印：AB827；Package：TSSOP；10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

文件：519.58 Kbytes 页数：19 Pages

TI2

德州仪器

丝印：AB827；Package：TSSOP；10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

文件：519.58 Kbytes 页数：19 Pages

TI2

德州仪器

丝印：AB827；Package：TSSOP；10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce)

文件：519.58 Kbytes 页数：19 Pages

TI2

德州仪器