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A67L0636E-3.8F中文资料欧密格数据手册PDF规格书
A67L0636E-3.8F规格书详情
General Description
The AMIC Zero Bus Latency (ZeBLTM) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process.
The A67L1618, A67L0636 SRAMs integrate a 2M X 18, 1M X 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. These SRAMs are optimized for 100 percent bus utilization without the insertion of any wait cycles during Write-Read alternation.
Features
■ Fast access time: 2.6/2.8/3.2/3.5/3.8/4.2 (250/227/200/166/150/133MHz)
■ Zero Bus Latency between READ and WRITE cycles allows 100 bus utilization
■ Signal +3.3V ± 5 power supply
■ Individual Byte Write control capability
■ Clock enable ( CEN) pin to enable clock and suspend operations
■ Clock-controlled and registered address, data and control signals
■ Registered output for pipelined applications
■ Three separate chip enables allow wide range of options for CE control, address pipelining
■ Internally self-timed write cycle
■ Selectable BURST mode (Linear or Interleaved)
■ SLEEP mode (ZZ pin) provided
■ Available in 100 pin LQFP package
产品属性
- 型号:
A67L0636E-3.8F
- 制造商:
AMICC
- 制造商全称:
AMIC Technology
- 功能描述:
2M X 18, 1M X 36 LVTTL, Pipelined ZeBL SRAM
供应商 | 型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
---|---|---|---|---|---|---|---|
AMICC |
23+ |
原厂原包 |
19960 |
只做进口原装 终端工厂免费送样 |
询价 |