2:12 Clock Multiplexer for PCIe Gen1–5 and UPI

Features ▪ 12 Low-power HCSL (LP-HCSL) outputs ▪ Integrated terminations for 85Ω (9ZXL1255/56) and 100Ω (9ZXL1245) systems eliminate up to 4 resistors per output pair ▪ Flexible Power Sequencing (FPS) configuration via SMBus ▪ Power Down Tolerant input (PDT); inputs: SEL_A_B#, SADR[1:0]_tri,

文件：805.45 Kbytes 页数：29 Pages

RENESAS

瑞萨

2:12 Clock Multiplexer for PCIe Gen1–5 and UPI

Features ▪ 12 Low-power HCSL (LP-HCSL) outputs ▪ Integrated terminations for 85Ω (9ZXL1255/56) and 100Ω (9ZXL1245) systems eliminate up to 4 resistors per output pair ▪ Flexible Power Sequencing (FPS) configuration via SMBus ▪ Power Down Tolerant input (PDT); inputs: SEL_A_B#, SADR[1:0]_tri,

文件：805.45 Kbytes 页数：29 Pages

RENESAS

瑞萨

2:12 Clock Multiplexer for PCIe Gen1–5 and UPI

Features ▪ 12 Low-power HCSL (LP-HCSL) outputs ▪ Integrated terminations for 85Ω (9ZXL1255/56) and 100Ω (9ZXL1245) systems eliminate up to 4 resistors per output pair ▪ Flexible Power Sequencing (FPS) configuration via SMBus ▪ Power Down Tolerant input (PDT); inputs: SEL_A_B#, SADR[1:0]_tri,

文件：805.45 Kbytes 页数：29 Pages

RENESAS

瑞萨

VFQFPN-72

RENESAS(瑞萨)/IDT

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