3.3V PCIe Gen1–5 Clock Generator Family

Features ▪ Integrated terminations for 100Ω and 85Ω systems save 4 resistors per output ▪ 112–206 mW typical power consumption (at 3.3V) ▪ VDDIO rail allows 35 power savings at optional 1.05V (9FGL06 and 9FGL08 only) ▪ Devices contain default configuration; SMBus not required ▪ SMBus-select

文件：1.35998 Mbytes 页数：37 Pages

RENESAS

瑞萨

Package：24-VFQFN 裸露焊盘；包装：卷带（TR） 类别：集成电路（IC） 应用特定时钟/定时 描述：IC CLK GENERATOR PCIE 24VFQFPN

Renesas Electronics America Inc

2-output 3.3V PCIe Clock Generator

文件：370.47 Kbytes 页数：19 Pages

IDT

2-output 3.3V PCIe Clock Generator

文件：370.47 Kbytes 页数：19 Pages

IDT

3.3V PCIe Gen1–5 Clock Generator Family

Features ▪ Integrated terminations for 100Ω and 85Ω systems save 4 resistors per output ▪ 112–206 mW typical power consumption (at 3.3V) ▪ VDDIO rail allows 35 power savings at optional 1.05V (9FGL06 and 9FGL08 only) ▪ Devices contain default configuration; SMBus not required ▪ SMBus-select

文件：1.35998 Mbytes 页数：37 Pages

RENESAS

瑞萨