9DB1933中文资料19-output Differential Buffer For PCIe Gen3数据手册Renesas规格书

描述 Description

The 9DB1933 zero-delay buffer supports PCIe Gen3 requirements, while being backwards compatible to PCIe Gen2 and Gen1. The 9DB1933 is driven by a differential SRC output pair from an IDT 932S421, 932SQ420, or equivalent, main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without Spread-Spectrum clocking.

特性 Features

• 19 - 0.7 V current mode differential HCSL output pairs
• 11 dedicated and 3 group OE# pins/Hardware control of the outputs
• Selectable PLL bandwidth/minimizes jitter peaking in downstream PLL's
• SMBus Interface, unused outputs can be disabled
• Cycle-to-cycle jitter <50 ps
• PCIe Gen3 phase jitter < 1.0 ps RMS