8V19N470数据手册集成电路（IC）的时钟发生器PLL频率合成器规格书PDF

描述 Description

The 8V19N470 is a fully integrated FemtoClock® NG jitter attenuator and clock synthesizer designed as a high-performance clock solution for conditioning and frequency/phase management of wireless base station radio equipment boards. The device is optimized to deliver excellent phase noise performance as required in GSM, WCDMA, LTE, LTE-A radio board implementations.

A two-stage PLL architecture supports both jitter attenuation and frequency multiplication. The first stage PLL is the jitter attenuator and uses an external VCXO for best possible phase noise characteristics. The second stage PLL locks on the VCXO-PLL output signal and synthesizes the target frequency. This PLL has two VCO circuits at 2949.12MHz and 2400MHz – 2500MHz, respectively, for enhanced frequency flexibility.

The device generates the output clock signals from the selected VCO by frequency division. Four independent integer frequency dividers are available. Delay circuits can be used for achieving alignment and controlled phase delay between clock signals. The two redundant inputs are monitored for activity. Four selectable clockswitching modes are provided to handle clock input failure scenarios. Auto-lock, individually programmable output frequency dividers and phase adjustment capabilities are added for flexibility. The device is configured through an SPI interface and reports PLL lock and signal loss status in internal registers, PLL lock status is also reported via two lock detect outputs. Internal status bit changes can also be reported via the nINT output. The device is ideal for driving converter circuits in wireless infrastructure, radar/imaging and instrumentation/medical applications.

For information regarding evaluation boards and material, please contact your local sales representative.

特性 Features

• High-performance clock RF-PLL
• Optimized for low phase noise: ≤150dBc/Hz (1MHz offset; 245.76MHz clock)
• Dual-PLL architecture
• 1st-PLL stage with external VCXO for clock jitter attenuation
• 2nd-PLL stage with internal FemtoClock NG PLL at selectable 2949.12MHz and 2400MHz - 2500MHz VCO

应用 Application

• Satellite Communications
• X-Band Radar
• 数字示波器中的时钟需求