丝印：8S73034AMIL；Package：SOIC；Low Skew, ÷2, ÷4, ÷8 Differential-to-LVPECL Clock Divider

Features • ÷2, ÷4 and ÷8 clock frequency divider • Three differential LVPECL output pairs • One differential PCLK, nPCLK input pair • PCLK, nPCLK pair can accept the following differential input levels: LVPECL, LVDS, CML • VBB bias voltage generator supports single-ended LVPECL clock input

文件：1.08092 Mbytes 页数：21 Pages

RENESAS

瑞萨

丝印：8S73034AMIL；Package：SOIC；Low Skew, ÷2, ÷4, ÷8 Differential-to-LVPECL Clock Divider

Features • ÷2, ÷4 and ÷8 clock frequency divider • Three differential LVPECL output pairs • One differential PCLK, nPCLK input pair • PCLK, nPCLK pair can accept the following differential input levels: LVPECL, LVDS, CML • VBB bias voltage generator supports single-ended LVPECL clock input

文件：1.08092 Mbytes 页数：21 Pages

RENESAS

瑞萨

丝印：8S73034AMIL；Package：SOIC；Low Skew, ÷2, ÷4, ÷8 Differential-to-LVPECL Clock Divider

Features • ÷2, ÷4 and ÷8 clock frequency divider • Three differential LVPECL output pairs • One differential PCLK, nPCLK input pair • PCLK, nPCLK pair can accept the following differential input levels: LVPECL, LVDS, CML • VBB bias voltage generator supports single-ended LVPECL clock input

文件：1.08092 Mbytes 页数：21 Pages

RENESAS

瑞萨

丝印：8S73034AMIL；Package：SOIC；Low Skew, ÷2, ÷4, ÷8 Differential-to-LVPECL Clock Divider

Features • ÷2, ÷4 and ÷8 clock frequency divider • Three differential LVPECL output pairs • One differential PCLK, nPCLK input pair • PCLK, nPCLK pair can accept the following differential input levels: LVPECL, LVDS, CML • VBB bias voltage generator supports single-ended LVPECL clock input

文件：1.08092 Mbytes 页数：21 Pages

RENESAS

瑞萨