Programmable Low Additive Jitter 2:8 Buffer with Dividers and Universal Outputs

Description The device is intended to take 1 or 2 reference clocks, select between them, using a pin or register selection and generate up to 8 outputs that may be the same as the reference frequency or integer-divider versions of it. The 8P79818 supports two output banks, each with its own d

文件：1.18054 Mbytes 页数：34 Pages

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Programmable Low Additive Jitter 2:8 Buffer with Dividers and Universal Outputs

文件：869.64 Kbytes 页数：34 Pages

IDT

Programmable Low Additive Jitter 2:8 Buffer with Dividers and Universal Outputs

The device is intended to take 1 or 2 reference clocks, select between them, using a pin or register selection and generate up to 8 outputs that may be the same as the reference frequency or integer-divider versions of it.\n\nThe 8P79818 supports two output banks, each with its own divider and power • Two differential inputs support LVPECL, LVDS, HCSL or LVCMOS reference clocks\n• Select which of the two input clocks is to be used as the reference clock for which divider via pin or register selection\n• Generates eight differential outputs or eight LVCMOS outputs, LVCMOS on Bank A only\n• Outpu;

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瑞萨

Programmable Low Additive Jitter 2:8 Buffer with Dividers and Universal Outputs

Description The device is intended to take 1 or 2 reference clocks, select between them, using a pin or register selection and generate up to 8 outputs that may be the same as the reference frequency or integer-divider versions of it. The 8P79818 supports two output banks, each with its own d

文件：1.18054 Mbytes 页数：34 Pages

RENESAS

瑞萨

Programmable Low Additive Jitter 2:8 Buffer with Dividers and Universal Outputs

Description The device is intended to take 1 or 2 reference clocks, select between them, using a pin or register selection and generate up to 8 outputs that may be the same as the reference frequency or integer-divider versions of it. The 8P79818 supports two output banks, each with its own d

文件：1.18054 Mbytes 页数：34 Pages

RENESAS

瑞萨

Programmable Low Additive Jitter 2:8 Buffer with Dividers and Universal Outputs

Description The device is intended to take 1 or 2 reference clocks, select between them, using a pin or register selection and generate up to 8 outputs that may be the same as the reference frequency or integer-divider versions of it. The 8P79818 supports two output banks, each with its own d

文件：1.18054 Mbytes 页数：34 Pages

RENESAS

瑞萨

Programmable Low Additive Jitter 2:8 Buffer with Dividers and Universal Outputs

Description The device is intended to take 1 or 2 reference clocks, select between them, using a pin or register selection and generate up to 8 outputs that may be the same as the reference frequency or integer-divider versions of it. The 8P79818 supports two output banks, each with its own d

文件：1.18054 Mbytes 页数：34 Pages

RENESAS

瑞萨

Programmable Low Additive Jitter 2:8 Buffer with Dividers and Universal Outputs

文件：869.64 Kbytes 页数：34 Pages

IDT

Programmable Low Additive Jitter 2:8 Buffer with Dividers and Universal Outputs

文件：869.64 Kbytes 页数：34 Pages

IDT

Programmable Low Additive Jitter 2:8 Buffer with Dividers and Universal Outputs

文件：869.64 Kbytes 页数：34 Pages

IDT