1:6 LVDS Output 1.8V Fanout Buffer

Features • Six low skew, low additive jitter LVDS output pairs • One differential clock input pair • Differential CLK, nCLK pair can accept the following differential input levels: LVDS, CML • Maximum input clock frequency: 1.2GHz (maximum) • Output skew: 20ps (typical) • Propagation delay:

文件：1.2356 Mbytes 页数：17 Pages

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1:6 LVDS Output 1.8V Fanout Buffer

The IDT 8P34S1106i is a high-performance differential LVDS fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. The 8P34S1106i is characterized to operate from a 1.8V power supply. Guaranteed output-to-output and part-to-part s • Six low skew, low additive jitter LVDS output pairs;

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1:6 LVDS Output 1.8V Fanout Buffer

Features • Six low skew, low additive jitter LVDS output pairs • One differential clock input pair • Differential CLK, nCLK pair can accept the following differential input levels: LVDS, CML • Maximum input clock frequency: 1.2GHz (maximum) • Output skew: 20ps (typical) • Propagation delay:

文件：1.2356 Mbytes 页数：17 Pages

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瑞萨

One differential clock input pair

文件：312.25 Kbytes 页数：18 Pages

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