8737-11中文资料Low Skew,÷1/÷2 Differential-to- 3.3V LVPECL Clock Generator数据手册Renesas规格书

描述 Description

The 8737-11 is a low skew, high performance Differential-to-3.3V LVPECL Clock Generator/Divider. The 8737-11 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels.The clock enable isinternally synchronized to eliminate runt pulses on theoutputs during asynchronous assertion/deassertion of the clock enable pin. Guaranteed output and part-to-part skew characteristics make the 8737-11 ideal for clock distribution applications demanding well defined performance and repeatability.

特性 Features

• 2 divide by 1 differential 3.3V LVPECL outputs
• Selectable differential CLK, nCLK or LVPECL clock inputs
• PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL
• Translates any single ended input signal (LVCMOS, LVTTL, GTL) to LVPECL levels with resistor bias on nCLK input
• Part-to-part skew: 200ps (maximum)
• Additive phase jitter, RMS: 0.04ps (typical)
• 3.3V operating supply
• Lead-Free package RoHS compliant