丝印：87354AIL；Package：SOIC；÷4/÷5 Differential-to-3.3V LVPECL Clock Generator

FEATURES • One differential 3.3V LVPECL output • One CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Maximum clock input frequency: 1GHz • Translates any single ended input signal (LVCMOS, LVTTL, GTL) to LVPECL lev

文件：359.17 Kbytes 页数：16 Pages

RENESAS

瑞萨

丝印：87354AIL；Package：SOIC；÷4/÷5 Differential-to-3.3V LVPECL Clock Generator

FEATURES • One differential 3.3V LVPECL output • One CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Maximum clock input frequency: 1GHz • Translates any single ended input signal (LVCMOS, LVTTL, GTL) to LVPECL lev

文件：359.17 Kbytes 页数：16 Pages

RENESAS

瑞萨

丝印：87354AIL；Package：SOIC；Differential-to-3.3V LVPECL Clock Generator

文件：198.44 Kbytes 页数：15 Pages

IDT

丝印：87354AIL；Package：SOIC；Differential-to-3.3V LVPECL Clock Generator

文件：198.44 Kbytes 页数：15 Pages

IDT