包装：散装 类别：标签，标志，护栏，标识 标签 描述：TAG BRASS RND 1.5 DCWR 201-225

Brady Corporation

包装：散装 类别：标签，标志，护栏，标识 标签 描述：TAG BRASS RND 1.5 DCWR 201-225

Brady Corporation

丝印：ICS7339AI11L；Package：TSSOP；Low Skew, ÷2/4,÷4/5/6, Differential-to-3.3V LVPECL Clock Generator

FEATURES • Dual ÷2, ÷4 differential 3.3V LVPECL outputs; Dual ÷4, ÷5, ÷6 differential 3.3V LVPECL outputs • One differential CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL • Maximum clock input frequency: 1GHz • Tra

文件：386.47 Kbytes 页数：16 Pages

RENESAS

瑞萨

丝印：ICS7339AI11L；Package：TSSOP；Low Skew, ÷2/4,÷4/5/6, Differential-to-3.3V LVPECL Clock Generator

FEATURES • Dual ÷2, ÷4 differential 3.3V LVPECL outputs; Dual ÷4, ÷5, ÷6 differential 3.3V LVPECL outputs • One differential CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL • Maximum clock input frequency: 1GHz • Tra

文件：386.47 Kbytes 页数：16 Pages

RENESAS

瑞萨

丝印：ICS7339AI11L；Package：SOIC；Low Skew, ÷2/4,÷4/5/6, Differential-to-3.3V LVPECL Clock Generator

FEATURES • Dual ÷2, ÷4 differential 3.3V LVPECL outputs; Dual ÷4, ÷5, ÷6 differential 3.3V LVPECL outputs • One differential CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL • Maximum clock input frequency: 1GHz • Tra

文件：386.47 Kbytes 页数：16 Pages

RENESAS

瑞萨

丝印：ICS7339AI11L；Package：SOIC；Low Skew, ÷2/4,÷4/5/6, Differential-to-3.3V LVPECL Clock Generator

FEATURES • Dual ÷2, ÷4 differential 3.3V LVPECL outputs; Dual ÷4, ÷5, ÷6 differential 3.3V LVPECL outputs • One differential CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL • Maximum clock input frequency: 1GHz • Tra

文件：386.47 Kbytes 页数：16 Pages

RENESAS

瑞萨

Low Skew, ÷2/4,÷4/5/6, Differential-to-3.3V LVPECL Clock Generator

FEATURES • Dual ÷2, ÷4 differential 3.3V LVPECL outputs; Dual ÷4, ÷5, ÷6 differential 3.3V LVPECL outputs • One differential CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL • Maximum clock input frequency: 1GHz • Tra

文件：386.47 Kbytes 页数：16 Pages

RENESAS

瑞萨

丝印：ICS7339AI11L；Package：TSSOP；Low Skew, Differential-to-3.3V LVPECL Clock Generator

文件：196.51 Kbytes 页数：15 Pages

IDT

丝印：ICS7339AI11L；Package：TSSOP；Low Skew, Differential-to-3.3V LVPECL Clock Generator

文件：196.51 Kbytes 页数：15 Pages

IDT

丝印：ICS7339AI11L；Package：SOIC；Low Skew, Differential-to-3.3V LVPECL Clock Generator

文件：196.51 Kbytes 页数：15 Pages

IDT