LVCMOS Clock Generator

The 870919I is an LVCMOS clock generator that uses an internal phase lock loop (PLL) for frequency multiplication and to lock the low-skew outputs to the selected reference clock. The device offers eight outputs. The PLL loop filter is completely internal and does not require external components. Se ·Two selectable single-ended input reference clocks\n·Eight single-ended clock outputs\n·Internal PLL does not require external loop filter components\n·5V tolerant inputs\n·Maximum output frequency: 160MHz, (2XQ output)\n·Maximum output frequency: 80MHz, (Q0:Q4 and nQ5 outputs)\n·LVCMOS interface l;

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LVCMOS Clock Generator

The 870919I-01 is an LVCMOS clock generator that uses an internal phase lock loop (PLL) for frequency multiplication and to lock the low-skew outputs to the selected reference clock. The device offers eight outputs. The PLL loop filter is completely internal and does not require external components. ·Two selectable single-ended input reference clocks\n·Eight single-ended clock outputs\n·Internal PLL does not require external loop filter components\n·5V tolerant inputs\n·Maximum output frequency: 160MHz, (2XQ output)\n·Maximum output frequency: 80MHz, (Q0:Q4 and nQ5 outputs)\n·LVCMOS interface l;

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LVCMOS Clock Generator

Features • Two selectable single-ended input reference clocks • Eight single-ended clock outputs • Internal PLL does not require external loop filter components • 5V tolerant inputs • Maximum output frequency: 160MHz, (2XQ output) • Maximum output frequency: 80MHz, (Q0:Q4 and nQ5 outputs) •

文件：378.89 Kbytes 页数：16 Pages

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瑞萨

LVCMOS Clock Generator

Features • Two selectable single-ended input reference clocks • Eight single-ended clock outputs • Internal PLL does not require external loop filter components • 5V tolerant inputs • Maximum output frequency: 160MHz, (2XQ output) • Maximum output frequency: 80MHz, (Q0:Q4 and nQ5 outputs) •

文件：428 Kbytes 页数：18 Pages

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