ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR

文件：183.45 Kbytes 页数：18 Pages

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Output frequency range

文件：276.24 Kbytes 页数：18 Pages

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Zero Delay, Differential-to-LVCMOS/ LVTTL Clock Generator

FEATURES • Eight LVCMOS/LVTTL outputs, 7Ω typical output impedance • Selectable CLK1, nCLK1 or LVCMOS/LVTTL clock inputs • CLK1, nCLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • CLK0 input accepts LVCMOS or LVTTL input levels • Output frequenc

文件：478.94 Kbytes 页数：19 Pages

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