Package：24-TSSOP（0.173"，4.40mm 宽）；包装：卷带（TR） 类别：集成电路（IC） 时钟发生器，PLL，频率合成器 描述：IC CLOCK GEN ZD 1:4 24-TSSOP

Renesas Electronics America Inc

Package：24-TSSOP（0.173"，4.40mm 宽）；包装：卷带（TR） 类别：集成电路（IC） 时钟发生器，PLL，频率合成器 描述：IC CLOCK GEN ZD 1:4 24-TSSOP

Renesas Electronics America Inc

1:4, Differential-to-LVCMOS/LVT

Features • Four LVCMOS/LVTTL outputs, 7Ω typical output impedance • Selectable CLK0/nCLK0 or CLK1/nCLK1 clock inputs • CLKx/nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Internal bias on nCLK0 and nCLK1 to support LVCMOS/LVTTL levels on CL

文件：829.71 Kbytes 页数：16 Pages

RENESAS

瑞萨

1:4, Differential-to-LVCMOS/LVT

Features • Four LVCMOS/LVTTL outputs, 7Ω typical output impedance • Selectable CLK0/nCLK0 or CLK1/nCLK1 clock inputs • CLKx/nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Internal bias on nCLK0 and nCLK1 to support LVCMOS/LVTTL levels on CL

文件：829.71 Kbytes 页数：16 Pages

RENESAS

瑞萨

1:4, Differential-to-LVCMOS/LVT

Features • Four LVCMOS/LVTTL outputs, 7Ω typical output impedance • Selectable CLK0/nCLK0 or CLK1/nCLK1 clock inputs • CLKx/nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Internal bias on nCLK0 and nCLK1 to support LVCMOS/LVTTL levels on CL

文件：829.71 Kbytes 页数：16 Pages

RENESAS

瑞萨