85411数据手册集成电路（IC）的时钟缓冲器驱动器规格书PDF

描述 Description

The 85411 is a low skew, high performance 1-to-2 Differential-to-LVDS Fanout Buffer and a member of the family of High Performance Clock Solutions from IDT. The CLK, nCLK pair can accept most standard differential input levels.The 85411 is characterized to operate from a 3.3V power supply. Guaranteed output and part-to-part skew characteristics make the 85411 ideal for those clock distribution applications demanding well defined performance and repeatability.

特性 Features

• Two differential LVDS outputs
• One differential CLK, nCLK clock input
• CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
• Maximum output frequency: 650MHz
• Translates any single ended input signal to LVDS levels with resistor bias on nCLK input
• Output skew: 20ps (maximum)
• Part-to-part skew: 250ps (maximum)
• Additive phase jitter, RMS: 0.05ps (typical)
• Propagation delay: 2.5 ns (maximum)
• 3.3V operating supply
• 0°C to 70°C ambient operating temperature
• Available in lead free (RoHS 6) package