854104数据手册集成电路（IC）的时钟缓冲器驱动器规格书PDF

描述 Description

The 854104 is a low skew, high performance 1-to-4 Differential-to-LVDS Clock Fanout Buffer and a member of the HiPerClockS™ family of High Performance Clock Solutions from IDT. Utilizing Low Voltage Differential Signaling (LVDS), the 854104 provides a low power, low noise, solution for distributing clock signals over controlled impedances of 100?. The 854104 accepts a differential input level and translates it to LVDS output levels. Guaranteed output and part-to-part skew characteristics make the 854104 ideal for those applications demanding well defined performance and repeatability.

特性 Features

• Four differential LVDS output pairs
• One differential clock input pair
• CLK/nCLK can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
• Each output has an individual OE control
• Maximum output frequency: 700MHz
• Translates differential input signals to LVDS levels
• Additive phase jitter, RMS: 0.232ps (typical)
• Output skew: 50ps (maximum)
• Part-to-part skew: 350ps (maximum)
• Propagation delay: 1.3ns (maximum)
• 3.3V operating supply
• 0°C to 70°C ambient operating temperature
• Available in lead-free (RoHS 6) packages

简介

854104属于集成电路（IC）的时钟缓冲器驱动器。由制造生产的854104时钟缓冲器，驱动器时钟缓冲器和驱动器集成电路产品族中的产品用于帮助信号在系统中传输，常用作频率/时间参考信号，以同步系统内的活动。尽管这些器件最常用到的功能就是缓冲（即，为使信号不受驱动负载的影响而从某个信号源复制信号），但是该产品族中的某些器件还能执行其他功能，例如选择性改变缓冲信号路径、按某个整数值分割信号频率，或进行所用电信号格式转换。