85408BGILFT集成电路（IC）的时钟缓冲器驱动器规格书PDF中文资料

特性 Features

• Eight differential LVDS output pairs

• One differential clock input pair

• CLK, nCLK can accept the following differential input levels:

LVPECL, LVDS, LVHSTL, HCSL, SSTL

• Maximum output frequency: 700MHz

• Translates any differential input signal (LVPECL, LVHSTL, SSTL,

HCSL) to LVDS levels without external bias networks

• Translates any single-ended input signal to LVDS with resistor

bias on nCLK input

• Multiple output enable inputs for disabling unused outputs

in reduced fanout applications

• Additive phase jitter, RMS: 167fs (typical)

• Output skew: 50ps (maximum)

• Part-to-part skew: 550ps (maximum)

• Propagation delay: 2.4ns (maximum)

• 3.3V operating supply

• -40°C to 85°C ambient operating temperature

• Available in lead-free (RoHS 6) package