85408BGILFT

Low Skew, 1-to-8, Differential-to-LVDS Clock

Features •EightdifferentialLVDSoutputpairs •Onedifferentialclockinputpair •CLK,nCLKcanacceptthefollowingdifferentialinputlevels: LVPECL,LVDS,LVHSTL,HCSL,SSTL •Maximumoutputfrequency:700MHz •Translatesanydifferentialinputsignal(LVPECL,LVHSTL,SSTL, HCSL)to

85408BGILFT

Low Skew, 1-to-8 , Different ial-to-LVDS Clock

85408BGILFT

包装：卷带（TR） 封装/外壳：24-TSSOP（0.173"，4.40mm 宽） 类别：集成电路（IC） 时钟缓冲器，驱动器 描述：IC CLK BUFFER 1:8 700MHZ 24TSSOP

85408

LowSkew,1-to-8,Differential-to-LVDSClock

Features •EightdifferentialLVDSoutputpairs •CLK/nCLKcanacceptthefollowingdifferentialinputlevels: LVPECL,LVDS,LVHSTL,HCSL,SSTL •Maximumoutputfrequency:700MHz •Translatesanydifferentialinputsignal(LVPECL,LVHSTL,SSTL, HCSL)toLVDSlevelswithoutexternalbiasnetw

85408BGILF

LowSkew,1-to-8,Differential-to-LVDSClock

85408BGILF

LowSkew,1-to-8,Differential-to-LVDSClock

Features •EightdifferentialLVDSoutputpairs •Onedifferentialclockinputpair •CLK,nCLKcanacceptthefollowingdifferentialinputlevels: LVPECL,LVDS,LVHSTL,HCSL,SSTL •Maximumoutputfrequency:700MHz •Translatesanydifferentialinputsignal(LVPECL,LVHSTL,SSTL, HCSL)to

85408BGLF

LowSkew,1-to-8,Differential-to-LVDSClock

Features •EightdifferentialLVDSoutputpairs •CLK/nCLKcanacceptthefollowingdifferentialinputlevels: LVPECL,LVDS,LVHSTL,HCSL,SSTL •Maximumoutputfrequency:700MHz •Translatesanydifferentialinputsignal(LVPECL,LVHSTL,SSTL, HCSL)toLVDSlevelswithoutexternalbiasnetw

85408BGLF

LowSkew,1-to-8,Differential-to-LVDSClock

85408BGLFT

LowSkew,1-to-8,Differential-to-LVDSClock

Features •EightdifferentialLVDSoutputpairs •CLK/nCLKcanacceptthefollowingdifferentialinputlevels: LVPECL,LVDS,LVHSTL,HCSL,SSTL •Maximumoutputfrequency:700MHz •Translatesanydifferentialinputsignal(LVPECL,LVHSTL,SSTL, HCSL)toLVDSlevelswithoutexternalbiasnetw

85408BGLFT

LowSkew,1-to-8,Differential-to-LVDSClock

85408I

LowSkew,1-to-8,Differential-to-LVDSClock

85408I

LowSkew,1-to-8,Differential-to-LVDSClock

Features •EightdifferentialLVDSoutputpairs •Onedifferentialclockinputpair •CLK,nCLKcanacceptthefollowingdifferentialinputlevels: LVPECL,LVDS,LVHSTL,HCSL,SSTL •Maximumoutputfrequency:700MHz •Translatesanydifferentialinputsignal(LVPECL,LVHSTL,SSTL, HCSL)to

ICS85408

LOWSKEW,1-TO-8DIFFERENTIAL-TO-LVDSCLOCKDISTRIBUTIONCHIP

GENERALDESCRIPTION TheICS85408isalowskew,highperformance1-to-8Differential-to-LVDSClockDistributionChipandamemberoftheHiPerClockS™familyofHighPerformanceClockSolutionsfromICS.TheICS85408CLK,nCLKpaircanacceptmostdifferentialinputlevelsandtranslatesthemto3

ICS85408BG

LOWSKEW,1-TO-8DIFFERENTIAL-TO-LVDSCLOCKDISTRIBUTIONCHIP

GENERALDESCRIPTION TheICS85408isalowskew,highperformance1-to-8Differential-to-LVDSClockDistributionChipandamemberoftheHiPerClockS™familyofHighPerformanceClockSolutionsfromICS.TheICS85408CLK,nCLKpaircanacceptmostdifferentialinputlevelsandtranslatesthemto3

ICS85408BGLF

LOWSKEW,1-TO-8DIFFERENTIAL-TO-LVDSCLOCKDISTRIBUTIONCHIP

GENERALDESCRIPTION TheICS85408isalowskew,highperformance1-to-8Differential-to-LVDSClockDistributionChipandamemberoftheHiPerClockS™familyofHighPerformanceClockSolutionsfromICS.TheICS85408CLK,nCLKpaircanacceptmostdifferentialinputlevelsandtranslatesthemto3

ICS85408BGLFT

LOWSKEW,1-TO-8DIFFERENTIAL-TO-LVDSCLOCKDISTRIBUTIONCHIP

GENERALDESCRIPTION TheICS85408isalowskew,highperformance1-to-8Differential-to-LVDSClockDistributionChipandamemberoftheHiPerClockS™familyofHighPerformanceClockSolutionsfromICS.TheICS85408CLK,nCLKpaircanacceptmostdifferentialinputlevelsandtranslatesthemto3

ICS85408BGT

LOWSKEW,1-TO-8DIFFERENTIAL-TO-LVDSCLOCKDISTRIBUTIONCHIP

GENERALDESCRIPTION TheICS85408isalowskew,highperformance1-to-8Differential-to-LVDSClockDistributionChipandamemberoftheHiPerClockS™familyofHighPerformanceClockSolutionsfromICS.TheICS85408CLK,nCLKpaircanacceptmostdifferentialinputlevelsandtranslatesthemto3

ICS85408I

LowSkew,1-to-8,Differential-to-LVDSClock