Low Skew, 1-to-4, Differential/LVCMOS-to- 0.7V HCSL Fanout Buffer

FEATURES • Four 0.7V differential HCSL outputs • Selectable differential CLK0, nCLK0 or LVCMOS inputs • CLK0, nCLK0 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL • CLK1 can accept the following input levels: LVCMOS or LVTTL • Maximum output frequency: 5

文件：419.88 Kbytes 页数：18 Pages

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瑞萨

Low Skew, 1-to-4, Differential/LVCMOS-to- 0.7V HCSL Fanout Buffer

文件：222.43 Kbytes 页数：17 Pages

IDT

Low Skew,1-to-4 Differential/LVCMOS-to-0.7V HCSL Fanout Buffer

The 85104I is a low skew, high performance 1-to-4 Differential/LVCMOS-to-0.7V HCSL Fanout Buffer. The 85104I has two selectable clock inputs. The CLK0, nCLK0 pair can accept most standard differential input levels. The single-ended CLK1 can accept LVCMOS or LVTTL input levels. The clock enable is in Four 0.7V differential HCSL outputs\nSelectable differential CLK0, nCLK0 or LVCMOS inputs\nCLK0, nCLK0 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL\nCLK1 can accept the following input levels: LVCMOS or LVTTL\nMaximum output frequency: 500MHz\nTranslates any si;

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瑞萨

Low Skew, 1-to-4, Differential/LVCMOS-to- 0.7V HCSL Fanout Buffer

文件：222.43 Kbytes 页数：17 Pages

IDT

Low Skew, 1-to-4, Differential/LVCMOS-to- 0.7V HCSL Fanout Buffer

FEATURES • Four 0.7V differential HCSL outputs • Selectable differential CLK0, nCLK0 or LVCMOS inputs • CLK0, nCLK0 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL • CLK1 can accept the following input levels: LVCMOS or LVTTL • Maximum output frequency: 5

文件：419.88 Kbytes 页数：18 Pages

RENESAS

瑞萨

Low Skew, 1-to-4, Differential/LVCMOS-to- 0.7V HCSL Fanout Buffer

文件：222.43 Kbytes 页数：17 Pages

IDT