Clock Generator For Cavium Processors

The 8413S06 is a PLL-based clock generator specifically designed for Cavium Networks Octeon II processors. This high performance device is optimized to generate the processor core reference clock, sRIO, XAUI, SGMII SerDes reference clocks and the clocks for both the Gigabit Ethernet MAC and PHY. The ·Six selectable 100MHz, 125MHz, 156.25MHz and 312.5MHzclocks for sRIO, XAUI, SGMII and HCSL interface levels\n·One 125MHz RGMII clock (QG), LVCMOS/LVTTL interface levels\n·One 50MHz processor core clock (QF), LVCMOS/LVTTL interface levels\n·Two 25MHz QREF clocks, LVCMOS/LVTTL interface levels, 15Ω o;

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Clock Generator for Cavium Processors

Six selectable 100MHz, 125MHz, 156.25MHz and 312.5MHz clocks for sRIO, XAUI, SGMII and HCSL interface levels One 125MHz RGMII clock (QG), LVCMOS/LVTTL interface levels One 50MHz processor core clock (QF), LVCMOS/LVTTL interface levels Two 25MHz QREF clocks, LVCMOS/LVTTL interface levels, 15

文件：1.56647 Mbytes 页数：31 Pages

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瑞萨

Clock Generator for Cavium Processors

Six selectable 100MHz, 125MHz, 156.25MHz and 312.5MHz clocks for sRIO, XAUI, SGMII and HCSL interface levels One 125MHz RGMII clock (QG), LVCMOS/LVTTL interface levels One 50MHz processor core clock (QF), LVCMOS/LVTTL interface levels Two 25MHz QREF clocks, LVCMOS/LVTTL interface levels, 15

文件：1.56647 Mbytes 页数：31 Pages

RENESAS

瑞萨

Clock Generator for Cavium Processors

Six selectable 100MHz, 125MHz, 156.25MHz and 312.5MHz clocks for sRIO, XAUI, SGMII and HCSL interface levels One 125MHz RGMII clock (QG), LVCMOS/LVTTL interface levels One 50MHz processor core clock (QF), LVCMOS/LVTTL interface levels Two 25MHz QREF clocks, LVCMOS/LVTTL interface levels, 15

文件：1.56647 Mbytes 页数：31 Pages

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