Clock Switch for ATCA/AMC and PCIe Applications

Features • Clock switch for PCIe and ATCA/AMC applications • Supports local and common ATCA/AMC clock modes • Bi-directional clock I/O FCLK: - When operating as an output, FCLK is a source-terminated HCSL signal. - When operating as an input, FCLK accepts HCSL, LVDS and LVPECL levels. • Lo

文件：680.27 Kbytes 页数：19 Pages

RENESAS

瑞萨

Clock Switch for ATCA/AMC and PCIe Applications

文件：484.92 Kbytes 页数：18 Pages

IDT

丝印：31752AIL；Package：TSSOP；Clock Switch for ATCA/AMC and PCIe Applications

Features • Clock switch for PCIe and ATCA/AMC applications • Supports local and common ATCA/AMC clock modes • Bi-directional clock I/O FCLK: - When operating as an output, FCLK is a source-terminated HCSL signal. - When operating as an input, FCLK accepts HCSL, LVDS and LVPECL levels. • Lo

文件：680.27 Kbytes 页数：19 Pages

RENESAS

瑞萨

丝印：31752AIL；Package：TSSOP；Clock Switch for ATCA/AMC and PCIe Applications

Features • Clock switch for PCIe and ATCA/AMC applications • Supports local and common ATCA/AMC clock modes • Bi-directional clock I/O FCLK: - When operating as an output, FCLK is a source-terminated HCSL signal. - When operating as an input, FCLK accepts HCSL, LVDS and LVPECL levels. • Lo

文件：680.27 Kbytes 页数：19 Pages

RENESAS

瑞萨

Clock Switch for ATCA/AMC and PCIe Applications

文件：484.92 Kbytes 页数：18 Pages

IDT

Clock Switch for ATCA/AMC and PCIe Applications

文件：484.92 Kbytes 页数：18 Pages

IDT

Clock Switch for ATCA/AMC and PCIe Applications

文件：484.92 Kbytes 页数：18 Pages

IDT

Clock Switch For ATCA/AMC And PCIe Applications

The 831752I is a high-performance, differential HCSL clock switch. The device is designed for the routing of PCIe clock signals in ATCA/AMC system and is optimized for PCIe Gen 1, Gen 2 and Gen 3. The device has one differential, bi-directional I/O (FCLK) for connection to ATCA clock sources and to ·Clock switch for PCIe and ATCA/AMC applications\n·Supports local and common ATCA/AMC clock modes\n·Bi-directional clock I/O FCLK: -When operating as an output, FCLK is a source-terminated HCSL signal. - When operating as an input, FCLK accepts HCSL, LVDS and LVPECL levels.\n·Local clock input (CLK);

Renesas

瑞萨

Package：2-SMD，J 形引线；包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 类别：电感器，线圈，扼流圈 固定电感器 描述：FIXED IND 2.2UH 16A 6 MOHM SMD

Würth Elektronik

Package：16-TSSOP（0.173"，4.40mm 宽）；包装：托盘 类别：集成电路（IC） 时钟缓冲器，驱动器 描述：NETWORK TIMING

Renesas Electronics America Inc